[PATCH 1/2] drm/amd/pm: decouple the watermark table setting from socclk/uclk dpms
Evan Quan
evan.quan at amd.com
Mon Sep 21 02:49:47 UTC 2020
As they have no real dependence. And for Navi1x, the socclk/uclk dpms
are enabled after DAL initialization.
Change-Id: Ia66a92155aadff40e4e2e46edbedce840cfb57ca
Signed-off-by: Evan Quan <evan.quan at amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 2b529885b05b..002bae81b856 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1831,17 +1831,16 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
+ if (smu->disable_watermark)
+ return 0;
+
mutex_lock(&smu->mutex);
- if (!smu->disable_watermark &&
- smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
- smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
- ret = smu_set_watermarks_table(smu, clock_ranges);
+ ret = smu_set_watermarks_table(smu, clock_ranges);
- if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
- smu->watermarks_bitmap |= WATERMARKS_EXIST;
- smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
- }
+ if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
+ smu->watermarks_bitmap |= WATERMARKS_EXIST;
+ smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
}
mutex_unlock(&smu->mutex);
--
2.28.0
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