[PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
Alex Deucher
alexdeucher at gmail.com
Fri Sep 25 21:26:24 UTC 2020
On Fri, Sep 25, 2020 at 5:13 PM Matt Coffin <mcoffin13 at gmail.com> wrote:
>
> Thanks for the quick reply,
>
> Would it make sense, since there seem to be issues with both
> before/after initialization, to (temporarily?) add a module parameter
> for users so that they can switch between these two behaviors easily
> based on what works for them?
I'd rather work on a proper fix. module options tend to lead to more
problems than they solve as people tend blindly apply them.
Alex
>
> If so, if you can toss me a hint at what name for the param would make
> sense, I can take a crack at a patch for it, for debugging by the people
> in the issue on GitLab.
>
> Cheers, and thanks for the time,
> Matt
>
> GL issue for reference:
> https://gitlab.freedesktop.org/drm/amd/-/issues/1260
>
> On 9/25/20 3:09 PM, Alex Deucher wrote:
> > On Fri, Sep 25, 2020 at 5:05 PM Matt Coffin <mcoffin13 at gmail.com> wrote:
> >>
> >> Sorry to bother you guys, but trying to learn about some of these
> >> things, and I'm tracking the issue this relates to pretty closely on GitLab.
> >>
> >> What does DAL stand for in this context?
> >
> > DAL is the name of the display team within AMD.
> >
> > Alex
> >
> >>
> >> Thanks in advance for the help,
> >> Matt
> >>
> >> On 9/24/20 9:38 PM, Quan, Evan wrote:
> >>> [AMD Official Use Only - Internal Distribution Only]
> >>>
> >>> That(postpone SOCCLK/UCLK enablement) will be revised and added back after confirmed with DAL team.
> >>> For now, we just revert it to get around the screen flicker issue introduced.
> >>>
> >>> BR
> >>> Evan
> >>> -----Original Message-----
> >>> From: Alex Deucher <alexdeucher at gmail.com>
> >>> Sent: Thursday, September 24, 2020 9:01 PM
> >>> To: Quan, Evan <Evan.Quan at amd.com>
> >>> Cc: amd-gfx list <amd-gfx at lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher at amd.com>
> >>> Subject: Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
> >>>
> >>> On Thu, Sep 24, 2020 at 6:10 AM Evan Quan <evan.quan at amd.com> wrote:
> >>>>
> >>>> Revert the guilty change introduced by the commit below:
> >>>> drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL
> >>>> initialization(V2)
> >>>>
> >>>> Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
> >>>> Signed-off-by: Evan Quan <evan.quan at amd.com>
> >>>
> >>> Won't this effectively disable the potential fix for multiple monitors at boot time?
> >>>
> >>> Acked-by: Alex Deucher <alexander.deucher at amd.com>
> >>>
> >>>> ---
> >>>> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++++++-------------
> >>>> 1 file changed, 12 insertions(+), 31 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >>>> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >>>> index 1695b36dc23c..be44cb941e73 100644
> >>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >>>> @@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> >>>> if (smu->dc_controlled_by_gpio)
> >>>> *(uint64_t *)feature_mask |=
> >>>> FEATURE_MASK(FEATURE_ACDC_BIT);
> >>>>
> >>>> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> >>>> + *(uint64_t *)feature_mask |=
> >>>> + FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> >>>> +
> >>>> + /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> >>>> + if (!(is_asic_secure(smu) &&
> >>>> + (adev->asic_type == CHIP_NAVI10) &&
> >>>> + (adev->rev_id == 0)) &&
> >>>> + (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> >>>> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >>>> + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> >>>> + |
> >>>> + FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> >>>> +
> >>>> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
> >>>> if (is_asic_secure(smu) &&
> >>>> (adev->asic_type == CHIP_NAVI10) && @@ -2629,43 +2641,12
> >>>> @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
> >>>>
> >>>> static int navi10_post_smu_init(struct smu_context *smu) {
> >>>> - struct smu_feature *feature = &smu->smu_feature;
> >>>> struct amdgpu_device *adev = smu->adev;
> >>>> - uint64_t feature_mask = 0;
> >>>> int ret = 0;
> >>>>
> >>>> if (amdgpu_sriov_vf(adev))
> >>>> return 0;
> >>>>
> >>>> - /* For Naiv1x, enable these features only after DAL initialization */
> >>>> - if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> >>>> - feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> >>>> -
> >>>> - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> >>>> - if (!(is_asic_secure(smu) &&
> >>>> - (adev->asic_type == CHIP_NAVI10) &&
> >>>> - (adev->rev_id == 0)) &&
> >>>> - (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> >>>> - feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >>>> - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> >>>> - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> >>>> -
> >>>> - if (!feature_mask)
> >>>> - return 0;
> >>>> -
> >>>> - bitmap_or(feature->allowed,
> >>>> - feature->allowed,
> >>>> - (unsigned long *)(&feature_mask),
> >>>> - SMU_FEATURE_MAX);
> >>>> -
> >>>> - ret = smu_cmn_feature_update_enable_state(smu,
> >>>> - feature_mask,
> >>>> - true);
> >>>> - if (ret) {
> >>>> - dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");
> >>>> - return ret;
> >>>> - }
> >>>> -
> >>>> ret = navi10_run_umc_cdr_workaround(smu);
> >>>> if (ret) {
> >>>> dev_err(adev->dev, "Failed to apply umc cdr
> >>>> workaround!\n");
> >>>> --
> >>>> 2.28.0
> >>>>
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