[PATCH 07/45] drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2)

[Alex Deucher]

On Mon, Sep 28, 2020 at 4:52 PM Luben Tuikov <luben.tuikov at amd.com> wrote:
>
> On 2020-09-25 4:09 p.m., Alex Deucher wrote:
> > From: Huang Rui <ray.huang at amd.com>
> >
> > Van gogh only has one sdma.
> >
> > v2: use num_instances rather than APU flag
> >
> > Signed-off-by: Huang Rui <ray.huang at amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> > index 2077f897d6eb..8616d397da00 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> > @@ -289,7 +289,8 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
> >       *value = 0;
> >       for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
> >               en = &nv_allowed_read_registers[i];
> > -             if (reg_offset !=
> > +             if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
> > +                 reg_offset !=
>
> What is the significance here of the number 7?
>

7th register in the list (SOC15_REG_ENTRY(SDMA1, 0,
mmSDMA1_STATUS_REG) is not present on chips with one SDMA instance.

Alex

> Ah, notice here "sdma.num_instances" as opposed to "sdma.max_instances",
> how it makes sense, right?
>
> Regards,
> Luben
>
> >                   (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
> >                       continue;
> >
> >
>