[PATCH] drm/amd/pm: remove the "set" function of pp_dpm_mclk for vangogh
Huang Rui
ray.huang at amd.com
Wed Apr 14 06:34:36 UTC 2021
On Wed, Apr 14, 2021 at 02:20:10PM +0800, Du, Xiaojian wrote:
> This patch is to remove the "set" function of pp_dpm_mclk for vangogh.
> For vangogh, mclk bonds with fclk, they will lock each other
> on the same perfomance level. But according to the smu message from pmfw,
> only fclk is allowed to set value manually, so remove the unnecessary
> code of "set" function for mclk.
>
> Signed-off-by: Xiaojian Du <Xiaojian.Du at amd.com>
Acked-by: Huang Rui <ray.huang at amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 61ff9a663b21..35904315c1f9 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -1092,7 +1092,6 @@ static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
> return ret;
> break;
> case SMU_FCLK:
> - case SMU_MCLK:
> ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetHardMinFclkByFreq,
> min, NULL);
> @@ -1180,7 +1179,6 @@ static int vangogh_force_clk_levels(struct smu_context *smu,
> if (ret)
> return ret;
> break;
> - case SMU_MCLK:
> case SMU_FCLK:
> ret = vangogh_get_dpm_clk_limited(smu,
> clk_type, soft_min_level, &min_freq);
> @@ -1267,7 +1265,6 @@ static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
> SMU_SOCCLK,
> SMU_VCLK,
> SMU_DCLK,
> - SMU_MCLK,
> SMU_FCLK,
> };
>
> @@ -1296,7 +1293,6 @@ static int vangogh_unforce_dpm_levels(struct smu_context *smu)
> enum smu_clk_type clk_type;
> uint32_t feature;
> } clk_feature_map[] = {
> - {SMU_MCLK, SMU_FEATURE_DPM_FCLK_BIT},
> {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
> {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
> {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
> @@ -1428,7 +1424,6 @@ static int vangogh_set_performance_level(struct smu_context *smu,
> if (ret)
> return ret;
>
> - vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
> vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
> vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
> vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
> @@ -1468,7 +1463,6 @@ static int vangogh_set_performance_level(struct smu_context *smu,
> if (ret)
> return ret;
>
> - vangogh_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
> vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> --
> 2.25.1
>
More information about the amd-gfx
mailing list