[PATCH v3 5/6] drm/amd/display: Add DP 2.0 BIOS and DMUB Support
Kazlauskas, Nicholas
nicholas.kazlauskas at amd.com
Fri Aug 20 14:14:31 UTC 2021
On 2021-08-19 2:58 p.m., Fangzhi Zuo wrote:
> Parse DP2 encoder caps and hpo instance from bios
>
> Signed-off-by: Fangzhi Zuo <Jerry.Zuo at amd.com>
> ---
> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 10 ++++++++++
> drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 10 ++++++++++
> .../drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c | 4 ++++
> drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 6 ++++++
> drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++++
> .../gpu/drm/amd/display/include/bios_parser_types.h | 10 ++++++++++
> drivers/gpu/drm/amd/include/atomfirmware.h | 6 ++++++
> 7 files changed, 50 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
> index 6dbde74c1e06..cdb5c027411a 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
> @@ -1604,6 +1604,16 @@ static enum bp_result bios_parser_get_encoder_cap_info(
> ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
> info->HDMI_6GB_EN = (record->encodercaps &
> ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + info->IS_DP2_CAPABLE = (record->encodercaps &
> + ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0;
> + info->DP_UHBR10_EN = (record->encodercaps &
> + ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0;
> + info->DP_UHBR13_5_EN = (record->encodercaps &
> + ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0;
> + info->DP_UHBR20_EN = (record->encodercaps &
> + ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0;
> +#endif
> info->DP_IS_USB_C = (record->encodercaps &
> ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
>
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
> index f1f672a997d7..6e333b4af7d6 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
> @@ -340,6 +340,13 @@ static enum bp_result transmitter_control_v1_7(
> const struct command_table_helper *cmd = bp->cmd_helper;
> struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7 = {0};
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + uint8_t hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_0;
> +
> + if (dc_is_dp_signal(cntl->signal))
> + hpo_instance = (uint8_t)cntl->hpo_engine_id - ENGINE_ID_HPO_DP_0;
> +#endif
> +
> dig_v1_7.phyid = cmd->phy_id_to_atom(cntl->transmitter);
> dig_v1_7.action = (uint8_t)cntl->action;
>
> @@ -353,6 +360,9 @@ static enum bp_result transmitter_control_v1_7(
> dig_v1_7.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel);
> dig_v1_7.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
> dig_v1_7.connobj_id = (uint8_t)cntl->connector_obj_id.id;
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + dig_v1_7.HPO_instance = hpo_instance;
> +#endif
> dig_v1_7.symclk_units.symclk_10khz = cntl->pixel_clock/10;
>
> if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c
> index 46ea39f5ef8d..6f3c2fb60790 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c
> @@ -192,6 +192,10 @@ void dcn30_link_encoder_construct(
> enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
> bp_cap_info.DP_HBR3_EN;
> enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
> + enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE;
> + enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
> + enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
> + enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
Please drop the DCN guards around this section - don't want to modify
the bit field structure based on DCN vs DCE only.
> enc10->base.features.flags.bits.DP_IS_USB_C =
> bp_cap_info.DP_IS_USB_C;
> } else {
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
> index fa3a725e11dc..b99efcf4712f 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
> @@ -59,6 +59,12 @@ struct encoder_feature_support {
> uint32_t IS_TPS3_CAPABLE:1;
> uint32_t IS_TPS4_CAPABLE:1;
> uint32_t HDMI_6GB_EN:1;
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + uint32_t IS_DP2_CAPABLE:1;
> + uint32_t IS_UHBR10_CAPABLE:1;
> + uint32_t IS_UHBR13_5_CAPABLE:1;
> + uint32_t IS_UHBR20_CAPABLE:1;
> +#endif
Drop them here as well.
> uint32_t DP_IS_USB_C:1;
> } bits;
> uint32_t raw;
> diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> index 5950da7bf252..15c823c8ae93 100644
> --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> @@ -959,7 +959,11 @@ struct dmub_dig_transmitter_control_data_v1_7 {
> uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
> uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
> uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
> +#else
> uint8_t reserved0; /**< For future use */
> +#endif
> uint8_t reserved1; /**< For future use */
> uint8_t reserved2[3]; /**< For future use */
> uint32_t reserved3[11]; /**< For future use */
> diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
> index 76a87b682883..d2fb018d31d0 100644
> --- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
> +++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
> @@ -152,6 +152,10 @@ struct bp_transmitter_control {
> enum signal_type signal;
> enum dc_color_depth color_depth; /* not used for DCE6.0 */
> enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + enum tx_ffe_id txffe_sel; /* used for DCN3 */
> + enum engine_id hpo_engine_id; /* used for DCN3 */
> +#endif
> struct graphics_object_id connector_obj_id;
> /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
> * be pixel clock * deep_color_ratio (in KHz)
> @@ -319,6 +323,12 @@ struct bp_encoder_cap_info {
> uint32_t DP_HBR2_EN:1;
> uint32_t DP_HBR3_EN:1;
> uint32_t HDMI_6GB_EN:1;
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + uint32_t IS_DP2_CAPABLE:1;
> + uint32_t DP_UHBR10_EN:1;
> + uint32_t DP_UHBR13_5_EN:1;
> + uint32_t DP_UHBR20_EN:1;
> +#endif
And from this file as well.
> uint32_t DP_IS_USB_C:1;
> uint32_t RESERVED:27;
> };
> diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
> index 44955458fe38..d4b245f12651 100644
> --- a/drivers/gpu/drm/amd/include/atomfirmware.h
> +++ b/drivers/gpu/drm/amd/include/atomfirmware.h
> @@ -768,6 +768,12 @@ enum atom_encoder_caps_def
> ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
> ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
> ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> + ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board.
> + ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board
> + ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by board
> + ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported by board
> +#endif
And lastly from this file. We don't want to modify this shared header
with DAL specific guards.
Regards,
Nicholas Kazlauskas
> ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type.
> };
>
>
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