[PATCH V2 1/3] drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend

[Quan, Evan]

[Public]



> -----Original Message-----
> From: Chen, Guchun <Guchun.Chen at amd.com>
> Sent: Monday, August 23, 2021 4:44 PM
> To: Quan, Evan <Evan.Quan at amd.com>; amd-gfx at lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Lazar, Lijo
> <Lijo.Lazar at amd.com>; Zhu, James <James.Zhu at amd.com>; Liu, Leo
> <Leo.Liu at amd.com>; Pan, Xinhui <Xinhui.Pan at amd.com>
> Subject: RE: [PATCH V2 1/3] drm/amdgpu: add missing cleanups for Polaris12
> UVD/VCE on suspend
> 
> [Public]
> 
> Series is:
> Reviewed-by: Guchun Chen <guchun.chen at amd.com>
> 
> As we have rooted cause this issue, shall we revert former patch
> "drm/amdgpu: disable BACO support for 699F:C7 polaris12 SKU temporarily"?
[Quan, Evan] Yes, I will do that after those patches landed.

Thanks,
Evan
> 
> Regards,
> Guchun
> 
> -----Original Message-----
> From: Quan, Evan <Evan.Quan at amd.com>
> Sent: Monday, August 23, 2021 4:35 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Chen, Guchun
> <Guchun.Chen at amd.com>; Lazar, Lijo <Lijo.Lazar at amd.com>; Zhu, James
> <James.Zhu at amd.com>; Liu, Leo <Leo.Liu at amd.com>; Quan, Evan
> <Evan.Quan at amd.com>; Pan, Xinhui <Xinhui.Pan at amd.com>
> Subject: [PATCH V2 1/3] drm/amdgpu: add missing cleanups for Polaris12
> UVD/VCE on suspend
> 
> Perform proper cleanups on UVD/VCE suspend: powergate enablement,
> clockgating enablement and dpm disablement. This can fix some hangs
> observed on suspending when UVD/VCE still using(e.g. issue "pm-suspend"
> when video is still playing).
> 
> Change-Id: I36f39d9731e0a9638b52d5d92558b0ee9c23a9ed
> Signed-off-by: Evan Quan <evan.quan at amd.com>
> Signed-off-by: xinhui pan <xinhui.pan at amd.com>
> --
> v1->v2:
>   - move the changes to ->hw_fini() (James Zhu)
> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 24
> ++++++++++++++++++++++++  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> | 23 +++++++++++++++++++++++
>  2 files changed, 47 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 4eebf973a065..c238aa2014fb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -543,6 +543,30 @@ static int uvd_v6_0_hw_fini(void *handle)  {
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
> +	/*
> +	 * Proper cleanups before halting the HW engine:
> +	 *   - cancel the delayed idle work
> +	 *   - enable powergating
> +	 *   - enable clockgating
> +	 *   - disable dpm
> +	 *
> +	 * TODO: to align with the VCN implementation, move the
> +	 * jobs for clockgating/powergating/dpm setting to
> +	 * ->set_powergating_state().
> +	 */
> +	cancel_delayed_work_sync(&adev->uvd.idle_work);
> +
> +	if (adev->pm.dpm_enabled) {
> +		amdgpu_dpm_enable_uvd(adev, false);
> +	} else {
> +		amdgpu_asic_set_uvd_clocks(adev, 0, 0);
> +		/* shutdown the UVD block */
> +		amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
> +						       AMD_PG_STATE_GATE);
> +		amdgpu_device_ip_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
> +						       AMD_CG_STATE_GATE);
> +	}
> +
>  	if (RREG32(mmUVD_STATUS) != 0)
>  		uvd_v6_0_stop(adev);
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 6d9108fa22e0..e99877c13d5f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -490,6 +490,29 @@ static int vce_v3_0_hw_fini(void *handle)
>  	int r;
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
> +	/*
> +	 * Proper cleanups before halting the HW engine:
> +	 *   - cancel the delayed idle work
> +	 *   - enable powergating
> +	 *   - enable clockgating
> +	 *   - disable dpm
> +	 *
> +	 * TODO: to align with the VCN implementation, move the
> +	 * jobs for clockgating/powergating/dpm setting to
> +	 * ->set_powergating_state().
> +	 */
> +	cancel_delayed_work_sync(&adev->vce.idle_work);
> +
> +	if (adev->pm.dpm_enabled) {
> +		amdgpu_dpm_enable_vce(adev, false);
> +	} else {
> +		amdgpu_asic_set_vce_clocks(adev, 0, 0);
> +		amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_VCE,
> +						       AMD_PG_STATE_GATE);
> +		amdgpu_device_ip_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_VCE,
> +						       AMD_CG_STATE_GATE);
> +	}
> +
>  	r = vce_v3_0_wait_for_idle(handle);
>  	if (r)
>  		return r;
> --
> 2.29.0