[PATCH 5/8] drm/amdgpu/display: fix mixed declarations and code in dc_link_dp.c

[Alex Deucher]

Trivial.

Fixes: 808a662bb3a8 ("drm/amd/display: Add DP 2.0 SST DC Support")
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c   | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 0126e71841fa..2222929cbac0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2643,6 +2643,9 @@ bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_
 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
 {
 	struct dc_link_settings max_link_cap = {0};
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	enum dc_link_rate lttpr_max_link_rate;
+#endif
 
 	/* get max link encoder capability */
 	link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
@@ -2672,7 +2675,7 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link)
 			max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-		enum dc_link_rate lttpr_max_link_rate = get_lttpr_max_link_rate(link);
+		lttpr_max_link_rate = get_lttpr_max_link_rate(link);
 
 		if (lttpr_max_link_rate < max_link_cap.link_rate)
 			max_link_cap.link_rate = lttpr_max_link_rate;
@@ -4412,6 +4415,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
 {
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	uint8_t lttpr_dpcd_data[8];
+	bool allow_lttpr_non_transparent_mode = 0;
 #else
 	uint8_t lttpr_dpcd_data[6];
 #endif
@@ -4423,8 +4427,6 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
 	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-	bool allow_lttpr_non_transparent_mode = 0;
-
 	if ((link->dc->config.allow_lttpr_non_transparent_mode.bits.DP2_0 &&
 			link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)) {
 		allow_lttpr_non_transparent_mode = 1;
@@ -5926,13 +5928,12 @@ static void get_lane_status(
 	union lane_align_status_updated *status_updated)
 {
 	unsigned int lane;
+	uint8_t dpcd_buf[3] = {0};
 
 	if (status == NULL || status_updated == NULL) {
 		return;
 	}
 
-	uint8_t dpcd_buf[3] = {0};
-
 	core_link_read_dpcd(
 			link,
 			DP_LANE0_1_STATUS,
@@ -5957,6 +5958,9 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
 	bool result = false;
 	uint8_t req_slot_count = 0;
 	struct fixed31_32 avg_time_slots_per_mtp = { 0 };
+	union payload_table_update_status update_status = { 0 };
+	const uint32_t max_retries = 30;
+	uint32_t retries = 0;
 
 	if (allocate)	{
 		avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
@@ -5965,8 +5969,6 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
 		/// Leave req_slot_count = 0 if allocate is false.
 	}
 
-	union payload_table_update_status update_status = { 0 };
-
 	/// Write DPCD 2C0 = 1 to start updating
 	update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1;
 	core_link_write_dpcd(
@@ -5999,8 +6001,6 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
 
 	/// Poll till DPCD 2C0 read 1
 	/// Try for at least 150ms (30 retries, with 5ms delay after each attempt)
-	const uint32_t max_retries = 30;
-	uint32_t retries = 0;
 
 	while (retries < max_retries) {
 		if (core_link_read_dpcd(
-- 
2.31.1