[PATCH 1/1] drm/amdgpu: detach ring priority from gfx priority

[Das, Nirmoy]

On 8/26/2021 11:27 AM, Lazar, Lijo wrote:
>
>
> On 8/25/2021 9:12 PM, Nirmoy Das wrote:
>> Currently AMDGPU_RING_PRIO_MAX is redefinition of a
>> max gfx hwip priority, this won't work well when we will
>> have a hwip with different set of priorities than gfx.
>> Also, HW ring priorities are different from ring priorities.
>>
>> Create a global enum for ring priority levels which each
>> HWIP can use to define its own priority levels.
>>
>> Signed-off-by: Nirmoy Das <nirmoy.das at amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h  |  6 +++---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 10 ++++++++--
>>   2 files changed, 11 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> index d43fe2ed8116..937320293029 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> @@ -43,9 +43,9 @@
>>   #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
>>     enum gfx_pipe_priority {
>> -    AMDGPU_GFX_PIPE_PRIO_NORMAL = 1,
>> -    AMDGPU_GFX_PIPE_PRIO_HIGH,
>> -    AMDGPU_GFX_PIPE_PRIO_MAX
>> +    AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1,
>> +    AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2,
>> +    AMDGPU_GFX_PIPE_PRIO_MAX = AMDGPU_RING_PRIO_3
>
> Is this a valid priority level? If not, better avoid it.
>

Yes, it not. I will resend,  Thanks!

> Reviewed-by: Lijo Lazar <lijo.lazar at amd.com>
>
>>   };
>>     /* Argument for PPSMC_MSG_GpuChangeState */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>> index e713d31619fe..85541005c1ad 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>> @@ -36,8 +36,14 @@
>>   #define AMDGPU_MAX_VCE_RINGS        3
>>   #define AMDGPU_MAX_UVD_ENC_RINGS    2
>>   -#define AMDGPU_RING_PRIO_DEFAULT    1
>> -#define AMDGPU_RING_PRIO_MAX        AMDGPU_GFX_PIPE_PRIO_MAX
>> +enum amdgpu_ring_priority_level {
>> +    AMDGPU_RING_PRIO_0,
>> +    AMDGPU_RING_PRIO_1,
>> +    AMDGPU_RING_PRIO_DEFAULT = 1,
>> +    AMDGPU_RING_PRIO_2,
>> +    AMDGPU_RING_PRIO_3,
>> +    AMDGPU_RING_PRIO_MAX
>> +};
>>     /* some special values for the owner field */
>>   #define AMDGPU_FENCE_OWNER_UNDEFINED    ((void *)0ul)
>>