[PATCH] drm/amd/display: add dcn register DP_MSA_VBID_MISC for dcn1.x and dcn2.x

[Harry Wentland]

On 2021-08-26 12:59 p.m., Wu, Hersen wrote:
> [AMD Official Use Only]
> 
> 
> This patch add missing AMD ASIC register for DP programming in up stream.
> 
>  
> 
> From 05768b78865d9b41a1d35e9f8e34901321208f2a Mon Sep 17 00:00:00 2001
> 
> From: Hersen Wu hersenwu at amd.com <mailto:hersenwu at amd.com>
> 
> Date: Thu, 26 Aug 2021 12:49:08 -0400
> 
> Subject: [PATCH] drm/amd/display: add dcn register DP_MSA_VBID_MISC for dcn1.x
> 
> and dcn2.x
> 
>  
> 
> DP_MSA_VBID_MISC is missing in upstream. this register is needed
> 
> for DP programming.
> 
>  
> 
> Signed-off-by: Hersen Wu hersenwu at amd.com <mailto:hersenwu at amd.com>

Reviewed-by: Harry Wentland <harry.wentland at amd.com>

Harry

> 
> ---
> 
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 1 +
> 
> 1 file changed, 1 insertion(+)
> 
>  
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
> 
> index 0d86df97878c..35acb3342e31 100644
> 
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
> 
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
> 
> @@ -73,6 +73,7 @@
> 
>                SRI(HDMI_ACR_48_1, DIG, id),\
> 
>                SRI(DP_DB_CNTL, DP, id), \
> 
>                SRI(DP_MSA_MISC, DP, id), \
> 
> +             SRI(DP_MSA_VBID_MISC, DP, id), \
> 
>                SRI(DP_MSA_COLORIMETRY, DP, id), \
> 
>                SRI(DP_MSA_TIMING_PARAM1, DP, id), \
> 
>                SRI(DP_MSA_TIMING_PARAM2, DP, id), \
> 
> -- 
> 
> 2.17.1
>