[PATCH V4 1/1] drm/amdgpu: Disable PCIE_DPM on Intel RKL Platform

[Alex Deucher]

Applied.  Thanks!

Alex

On Mon, Aug 30, 2021 at 3:17 AM Koba Ko <koba.ko at canonical.com> wrote:
>
> Due to high latency in PCIE clock switching on RKL platforms,
> switching the PCIE clock dynamically at runtime can lead to HDMI/DP
> audio problems. On newer asics this is handled in the SMU firmware.
> For SMU7-based asics, disable PCIE clock switching to avoid the issue.
>
> AMD provide a parameter to disable PICE_DPM.
>
> modprobe amdgpu ppfeaturemask=0xfff7bffb
>
> It's better to contorl PCIE_DPM in amd gpu driver,
> switch PCI_DPM by determining intel RKL platform for SMU7-based asics.
>
> Fixes: 1a31474cdb48 ("drm/amd/pm: workaround for audio noise issue")
> Ref: https://lists.freedesktop.org/archives/amd-gfx/2021-August/067413.html
> Signed-off-by: Koba Ko <koba.ko at canonical.com>
> ---
>  .../gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> index 0541bfc81c1b..1d76cf7cd85d 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> @@ -27,6 +27,9 @@
>  #include <linux/pci.h>
>  #include <linux/slab.h>
>  #include <asm/div64.h>
> +#if IS_ENABLED(CONFIG_X86_64)
> +#include <asm/intel-family.h>
> +#endif
>  #include <drm/amdgpu_drm.h>
>  #include "ppatomctrl.h"
>  #include "atombios.h"
> @@ -1733,6 +1736,17 @@ static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
>         return result;
>  }
>
> +static bool intel_core_rkl_chk(void)
> +{
> +#if IS_ENABLED(CONFIG_X86_64)
> +       struct cpuinfo_x86 *c = &cpu_data(0);
> +
> +       return (c->x86 == 6 && c->x86_model == INTEL_FAM6_ROCKETLAKE);
> +#else
> +       return false;
> +#endif
> +}
> +
>  static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
>  {
>         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> @@ -1758,7 +1772,8 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
>
>         data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
>         data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
> -       data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
> +       data->pcie_dpm_key_disabled =
> +               intel_core_rkl_chk() || !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
>         /* need to set voltage control types before EVV patching */
>         data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
>         data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
> --
> 2.25.1
>