gpu block diagram

[Alex Deucher]

On Tue, Dec 7, 2021 at 5:07 PM Yann Dirson <ydirson at free.fr> wrote:
>
> Thanks for the details Alex!
>
> Here is an attempt to formalize the decomposition of a
> (mostly Renoir) APU, using plantuml.  That's highly preliminary,
> focusing on blocks/sub-blocks/firmware, based on my current
> partial (and surely incorrect at places) understanding.
> I focused on getting contents quickly, so the formalism itself
> is shaky.
>
> Can you spot any error ?  Fill those holes (usually marked with
> "?") ?  What additional blocks would make sense (caches at least,
> I guess) ?  What additional information would help understand how
> they work together (control/data flows, busses...) ?

Each asic is a collection of hardware blocks.  We refer to them as
"IPs" (Intellectual Property blocks).  Each IP encapsulates certain
functionality. IPs are versioned and can also be mixed and matched.
E.g., you might have two different asics that both have SDMA 5.x IPs.
The driver is arranged by IPs.  There are driver components to handle
the initialization and operation of each IP.  There are also a bunch
of smaller IPs that don't really need much if any driver interaction.
Those end up getting lumped into the common stuff in the soc files.
The soc files (e.g., vi.c, soc15.c nv.c) contain code for aspects of
the SoC itself rather than specific IPs.  E.g., things like GPU resets
and register access functions are SoC dependent.

An APU contains more than just CPU and GPU, it also contains all of
the platform stuff (audio, usb, gpio, etc.).  Also, a lot of
components are shared between the CPU, platform, and the GPU (e.g.,
SMU, PSP, etc.).  Specific components (CPU, GPU, etc.) usually have
their interface to interact with those common components.  For things
like S0i3 there is a ton of coordination required across all the
components, but that is probably a bit beyond the scope of this
thread.

With respect to the GPU, we have the following major IPs:

1. GMC (Graphics Memory Controller).  This was a dedicated IP on older
pre-vega chips, but has since become somewhat decentralized on vega
and newer chips.  They now have dedicated memory hubs for specific IPs
or groups of IPs.  We still treat it as a single component in the
driver however since the programming model is still pretty similar.
This is how the different IPs on the GPU get the memory (VRAM or
system memory).  It also provides the support for per process GPU
virtual address spaces.
2. IH (Interrupt Handler).  This is the interrupt controller on the
GPU.  All of the IPs feed their interrupts into this IP and it
aggregates them into a set of ring buffers that the driver can parse
to handle interrupts from different IPs.
3. PSP (Platform Security Processor).  This handles security policy
for the SoC and executes trusted applications, and validates and loads
firmwares for other blocks.
4. SMU (System Management Unit).  This is the power management
microcontroller.  It manages the entire SoC.  The driver interacts
with it to control power management features like clocks, voltages,
power rails, etc.
5. DCN (Display Controller Next).  This is the display controller.  It
handles the display hardware.
6. SDMA (System DMA).  This is a multi-purpose DMA engine.  The kernel
driver uses it for various things including paging and GPU page table
updates.  It's also exposed to userspace for use by user mode drivers
(OpenGL, Vulkan, etc.)
7. GC (graphics and Compute).  This is the graphics and compute
engine, i.e., the block that encompasses the 3D pipeline and and
shader blocks.  The is by far the largest block on the GPU.  The 3D
pipeline has tons of sub-blocks.  In addition to that, it also
contains the CP microcontrollers (ME, PFP, CE, MEC) and the RLC
microcontroller.  It's exposed to userspace for user mode drivers
(OpenGL, Vulkan, OpenCL, etc.)
7. VCN (Video Core Next).  This is the multi-media engine.  It handles
video and image encode and decode.  It's exposed to userspace for user
mode drivers (VA-API, OpenMAX, etc.)

In general, the driver has a list of all of the IPs on a particular
SoC and for things like init/fini/suspend/resume, more or less just
walks the list and handles each IP.

Alex


>
> Indentation is shaky too, better format it to read (e.g. by
> pasting in http://www.plantuml.com/plantuml/uml/)
>
> ------ >8 -------
> @startuml
> package "APU" {
>  package CPU {
>  }
>  package GPU {
>   package common? [[{"GPU Family"?}]] {
>   }
>   package GFX [[{Graphics and Compute Engine}]] {
>    package CP [[{Command Processor}]] {
>     package PFP [[{MicroEngine Compute}]] {
>       package "pfp fw" #cccccc {
>       }
>     }
>     package ME [[{MicroEngine ?}]] {
>       package "me fw" #cccccc {
>       }
>     }
>     package CE [[{?}]] {
>       package "ce fw" #cccccc {
>       }
>     }
>     package MEC [[{MicroEngine Compute}]] {
>       package "mec fw" #cccccc {
>       }
>       package "mec2 fw?" #cccccc {
>       }
>     }
>    }
>    package RLC [[{RunList Controller (pm)}]] {
>       package "rlc fw" #cccccc {
>       }
>    }
>   }
>
>   package '"management"'<<Cloud>>  {
>   package MES [[{Micro-Engine Scheduler}]] {
>   }
>   package SMU [[{System Mamagement Unit}]] {
>   }
>   package PSP [[{Platform Security Processor}]] {
>     package "asd fw" #cccccc {
>     }
>     package "ta fw" #cccccc {
>     }
>   }
>
>   package IH [[{Interrupt Handler}]] {
>   }
>   package GMC [[{Graphics Memory Controller}]] {
>   }
>   package SDMA [[{System DMA}]] {
>     package "sdma fw" #cccccc {
>     }
>   }
>   }
>
>   package DM [[{Display Manager, link to...}]] {
>    package "DMUB? DMU?" [[{Display Micro-Controller Unit}]] {
>     package "dmcub fw" #cccccc {
>     }
>    }
>    package ... {
>    }
>   }
>
>   package multimedia <<Cloud>> {
>    package .... {
>    }
>    package VCN {
>     package "vcn fw" #cccccc {
>     }
>    }
>    package JPEG {
>    }
>   }
>  }
> }
> @enduml
> ------ >8 -------