[PATCH 3/3] Documentation/gpu: include description of some of the GC microcontrollers

[Harry Wentland]

On 2021-12-09 18:47, Yann Dirson wrote:
> This is Alex' description from the "Looking for clarifications around gfx/kcq/kiq"
> thread, edited to fit as ReST.
> 
> Originally-by: Alex Deucher <alexander.deucher at amd.com>
> Signed-off-by: Yann Dirson <ydirson at free.fr>
> ---
>  Documentation/gpu/amdgpu/driver-core.rst | 35 ++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
> index 909b13fad6a8..453566c280c5 100644
> --- a/Documentation/gpu/amdgpu/driver-core.rst
> +++ b/Documentation/gpu/amdgpu/driver-core.rst
> @@ -75,6 +75,28 @@ VCN (Video Core Next)
>      decode.  It's exposed to userspace for user mode drivers (VA-API,
>      OpenMAX, etc.)
>  
> +Graphics and Compute microcontrollers
> +-------------------------------------
> +
> +CP (Command Processor)
> +    The name for the hardware block that encompasses the front end of the
> +    GFX/Compute pipeline.  Consists mainly of a bunch of microcontrollers
> +    (PFP, ME, CE, MEC).  The firmware that runs on these microcontrollers
> +    provides the driver interface to interact with the GFX/Compute engine.
> +
> +    MEC (MicroEngine Compute)
> +        The is the microcontroller that controls the compute queues on the

This should probably say "This is..." or "The MEC is..."

Again, really nice to see this. I can't vouch for the correctness of this
as this is outside my domain but it looks well enough to me.

Acked-by: Harry Wentland <harry.wentland at amd.com>

Harry

> +        GFX/compute engine.
> +
> +    MES (MicroEngine Scheduler)
> +        This is a new engine for managing queues.  This is currently unused.
> +
> +RLC (RunList Controller)
> +    This is another microcontroller in the GFX/Compute engine.  It handles
> +    power management related functionality within the GFX/Compute engine.
> +    The name is a vestige of old hardware where it was originally added
> +    and doesn't really have much relation to what the engine does now.
> +
>  Driver structure
>  ================
>  
> @@ -82,6 +104,19 @@ In general, the driver has a list of all of the IPs on a particular
>  SoC and for things like init/fini/suspend/resume, more or less just
>  walks the list and handles each IP.
>  
> +Some useful constructs:
> +
> +KIQ (Kernel Interface Queue)
> +    This is a control queue used by the kernel driver to manage other gfx
> +    and compute queues on the GFX/compute engine.  You can use it to
> +    map/unmap additional queues, etc.
> +
> +IB (Indirect Buffer)
> +    A command buffer for a particular engine.  Rather than writing
> +    commands directly to the queue, you can write the commands into a
> +    piece of memory and then put a pointer to the memory into the queue.
> +    The hardware will then follow the pointer and execute the commands in
> +    the memory, then returning to the rest of the commands in the ring.
>  
>  .. _amdgpu_memory_domains:
>  
>