[PATCH v2 3/3] Documentation/gpu: include description of some of the GC microcontrollers
Rodrigo Siqueira Jordao
rjordrigo at amd.com
Mon Dec 13 20:18:41 UTC 2021
On 2021-12-10 1:20 p.m., Yann Dirson wrote:
> This is Alex' description from the "Looking for clarifications around gfx/kcq/kiq"
> thread, edited to fit as ReST.
>
> Originally-by: Alex Deucher <alexander.deucher at amd.com>
> Signed-off-by: Yann Dirson <ydirson at free.fr>
> Acked-by: Harry Wentland <harry.wentland at amd.com>
> ---
> Documentation/gpu/amdgpu/driver-core.rst | 35 ++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
> index b870a63c64dd..942bc7c3eac9 100644
> --- a/Documentation/gpu/amdgpu/driver-core.rst
> +++ b/Documentation/gpu/amdgpu/driver-core.rst
> @@ -75,6 +75,28 @@ VCN (Video Core Next)
> decode. It's exposed to userspace for user mode drivers (VA-API,
> OpenMAX, etc.)
>
> +Graphics and Compute microcontrollers
> +-------------------------------------
/microcontrollers/Microcontrollers/
> +
> +CP (Command Processor)
> + The name for the hardware block that encompasses the front end of the
> + GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers
> + (PFP, ME, CE, MEC). The firmware that runs on these microcontrollers
> + provides the driver interface to interact with the GFX/Compute engine.
> +
> + MEC (MicroEngine Compute)
> + This is the microcontroller that controls the compute queues on the
> + GFX/compute engine.
> +
> + MES (MicroEngine Scheduler)
> + This is a new engine for managing queues. This is currently unused.
> +
> +RLC (RunList Controller)
> + This is another microcontroller in the GFX/Compute engine. It handles
> + power management related functionality within the GFX/Compute engine.
> + The name is a vestige of old hardware where it was originally added
> + and doesn't really have much relation to what the engine does now.
> +
> Driver structure
> ================
>
> @@ -82,6 +104,19 @@ In general, the driver has a list of all of the IPs on a particular
> SoC and for things like init/fini/suspend/resume, more or less just
> walks the list and handles each IP.
>
> +Some useful constructs:
> +
> +KIQ (Kernel Interface Queue)
> + This is a control queue used by the kernel driver to manage other gfx
> + and compute queues on the GFX/compute engine. You can use it to
> + map/unmap additional queues, etc.
> +
> +IB (Indirect Buffer)
> + A command buffer for a particular engine. Rather than writing
> + commands directly to the queue, you can write the commands into a
> + piece of memory and then put a pointer to the memory into the queue.
> + The hardware will then follow the pointer and execute the commands in
> + the memory, then returning to the rest of the commands in the ring.
>
> .. _amdgpu_memory_domains:
>
>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>
Thanks
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