[PATCH v2 2/2] drm/amd/amdgpu: fix gmc bo pin count leak in SRIOV

Christian König ckoenig.leichtzumerken at gmail.com
Tue Dec 14 13:02:45 UTC 2021


Am 14.12.21 um 05:17 schrieb Jingwen Chen:
> [Why]
> gmc bo will be pinned during loading amdgpu and reset in SRIOV while
> only unpinned in unload amdgpu
>
> [How]
> add amdgpu_in_reset and sriov judgement to skip pin bo
>
> v2: fix wrong judgement
>
> Signed-off-by: Jingwen Chen <Jingwen.Chen2 at amd.com>

Nirmoy already had a different patch set to stop unpin/pin on 
suspend/resume removing those code paths altogether.

He's just on parental leave right now, but I think those patches where 
ready and just needed testing.

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 ++++
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 4 ++++
>   2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index d696c4754bea..ae46eb35b3d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -992,10 +992,14 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
>   		return -EINVAL;
>   	}
>   
> +	if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
> +		goto skip_pin_bo;
> +
>   	r = amdgpu_gart_table_vram_pin(adev);
>   	if (r)
>   		return r;
>   
> +skip_pin_bo:
>   	r = adev->gfxhub.funcs->gart_enable(adev);
>   	if (r)
>   		return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index db2ec84f7237..d91eb7eb0ebe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -1717,10 +1717,14 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
>   		return -EINVAL;
>   	}
>   
> +	if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
> +		goto skip_pin_bo;
> +
>   	r = amdgpu_gart_table_vram_pin(adev);
>   	if (r)
>   		return r;
>   
> +skip_pin_bo:
>   	r = adev->gfxhub.funcs->gart_enable(adev);
>   	if (r)
>   		return r;



More information about the amd-gfx mailing list