[PATCH] drm/amdgpu/gfx10: update register offsets for VGH in the gfx_v10_0_setup_grbm_cam_remapping function

[Alex Deucher]

On Mon, Feb 1, 2021 at 4:07 AM chen gong <curry.gong at amd.com> wrote:
>

Missing patch description.

Also, nothing wrong with the change per se, but
gfx_v10_0_check_grbm_cam_remapping() returns true for vangogh, so
gfx_v10_0_setup_grbm_cam_remapping() is never called for vangogh.

Alex

> Signed-off-by: chen gong <curry.gong at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 56 +++++++++++++++++++++++++++++++++-
>  1 file changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 024460b..d7e9a18 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7031,9 +7031,63 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
>         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
>
>         switch (adev->asic_type) {
> +       case CHIP_VANGOGH:
> +               /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
> +               data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
> +                       GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> +                      (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Vangogh) <<
> +                       GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> +               /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
> +               data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
> +                       GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> +                      (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Vangogh) <<
> +                       GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> +               /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
> +               data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
> +                       GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> +                      (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Vangogh) <<
> +                       GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> +               /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
> +               data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
> +                       GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> +                      (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Vangogh) <<
> +                       GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> +               /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
> +               data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
> +                       GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> +                      (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Vangogh) <<
> +                       GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> +               /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
> +               data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
> +                       GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> +                      (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Vangogh) <<
> +                       GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
> +               WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
> +
> +               /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
> +               data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
> +                       GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
> +                      (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Vangogh) <<
> +                       GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
> +               break;
>         case CHIP_SIENNA_CICHLID:
>         case CHIP_NAVY_FLOUNDER:
> -       case CHIP_VANGOGH:
>         case CHIP_DIMGREY_CAVEFISH:
>                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
>                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
> --
> 2.7.4
>
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