[PATCH 3/4] drm/amdgpu: add INFO ioctl support for querying video caps (v3)

[Christian König]

Am 01.02.21 um 17:56 schrieb Alex Deucher:
> We currently hardcode these in mesa, but querying them from
> the kernel makes more sense since there may be board specific
> limitations that the kernel driver is better suited to
> determining.
>
> Userpace patches that use this interface:
> https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps
> https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps
>
> v2: reorder the codecs to better align with mesa
> v3: add max_pixels_per_frame to handle the portrait case, squash in
>      memory leak fix
>
> Reviewed-by: Leo Liu <leo.liu at amd.com> (v2)
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 58 +++++++++++++++++++++++++
>   include/uapi/drm/amdgpu_drm.h           | 34 +++++++++++++++
>   2 files changed, 92 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 3c37cf1ae8b7..390362beda0e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -983,6 +983,64 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
>   				min_t(u64, size, sizeof(ras_mask))) ?
>   			-EFAULT : 0;
>   	}
> +	case AMDGPU_INFO_VIDEO_CAPS: {
> +		const struct amdgpu_video_codecs *codecs;
> +		struct drm_amdgpu_info_video_caps *caps;
> +		int r;
> +
> +		switch (info->video_cap.type) {
> +		case AMDGPU_INFO_VIDEO_CAPS_DECODE:
> +			r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
> +			if (r)
> +				return -EINVAL;
> +			break;
> +		case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
> +			r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
> +			if (r)
> +				return -EINVAL;
> +			break;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("Invalid request %d\n",
> +				      info->video_cap.type);
> +			return -EINVAL;
> +		}
> +
> +		caps = kzalloc(sizeof(*caps), GFP_KERNEL);
> +		if (!caps)
> +			return -ENOMEM;
> +
> +		for (i = 0; i < codecs->codec_count; i++) {
> +			int idx = codecs->codec_array[i].codec_type;
> +
> +			switch (idx) {
> +			case AMDGPU_VIDEO_CODEC_TYPE_MPEG2:
> +			case AMDGPU_VIDEO_CODEC_TYPE_MPEG4:
> +			case AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC:
> +			case AMDGPU_VIDEO_CODEC_TYPE_VC1:
> +			case AMDGPU_VIDEO_CODEC_TYPE_HEVC:
> +			case AMDGPU_VIDEO_CODEC_TYPE_JPEG:
> +			case AMDGPU_VIDEO_CODEC_TYPE_VP9:
> +			case AMDGPU_VIDEO_CODEC_TYPE_AV1:
> +				caps->codec_info[idx].valid = 1;
> +				caps->codec_info[idx].max_width =
> +					codecs->codec_array[i].max_width;
> +				caps->codec_info[idx].max_height =
> +					codecs->codec_array[i].max_height;
> +				caps->codec_info[idx].max_pixels_per_frame =
> +					codecs->codec_array[i].max_pixels_per_frame;
> +				caps->codec_info[idx].max_level =
> +					codecs->codec_array[i].max_level;
> +				break;
> +			default:
> +				break;
> +			}
> +		}
> +		r = copy_to_user(out, caps,
> +				 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
> +		kfree(caps);
> +		return r;
> +	}
>   	default:
>   		DRM_DEBUG_KMS("Invalid request %d\n", info->query);
>   		return -EINVAL;
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 7fb9c09ee93f..728566542f8a 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -782,6 +782,12 @@ struct drm_amdgpu_cs_chunk_data {
>   #define AMDGPU_INFO_VRAM_LOST_COUNTER		0x1F
>   /* query ras mask of enabled features*/
>   #define AMDGPU_INFO_RAS_ENABLED_FEATURES	0x20
> +/* query video encode/decode caps */
> +#define AMDGPU_INFO_VIDEO_CAPS			0x21
> +	/* Subquery id: Decode */
> +	#define AMDGPU_INFO_VIDEO_CAPS_DECODE		0
> +	/* Subquery id: Encode */
> +	#define AMDGPU_INFO_VIDEO_CAPS_ENCODE		1
>   
>   /* RAS MASK: UMC (VRAM) */
>   #define AMDGPU_INFO_RAS_ENABLED_UMC			(1 << 0)
> @@ -878,6 +884,10 @@ struct drm_amdgpu_info {
>   		struct {
>   			__u32 type;
>   		} sensor_info;
> +
> +		struct {
> +			__u32 type;
> +		} video_cap;
>   	};
>   };
>   
> @@ -1074,6 +1084,30 @@ struct drm_amdgpu_info_vce_clock_table {
>   	__u32 pad;
>   };
>   
> +/* query video encode/decode caps */
> +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2			0
> +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4			1
> +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1			2
> +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC		3
> +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC			4
> +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG			5
> +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9			6
> +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1			7
> +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT			8

If I'm not completely mistaken this needs to be kept identical to the 
defines in amdgpu.h.

I think it might be better to have only one define for this.

Christian.

> +
> +struct drm_amdgpu_info_video_codec_info {
> +	__u32 valid;
> +	__u32 max_width;
> +	__u32 max_height;
> +	__u32 max_pixels_per_frame;
> +	__u32 max_level;
> +	__u32 pad;
> +};
> +
> +struct drm_amdgpu_info_video_caps {
> +	struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
> +};
> +
>   /*
>    * Supported GPU families
>    */