[PATCH v3] drm/amd/pm: enable DCS

[Nirmoy]

On 2/3/21 11:47 AM, Kenneth Feng wrote:
> Enable Async DCS


Please expand the commit message, like v1/v2 of this patch.


Regards,

Nirmoy


>
> V3:
> 1. add the flag to skip APU support.
> 2. remove the hunk for workload selection since
> it doesn't impact the function.
>
> Signed-off-by: Kenneth Feng <kenneth.feng at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c                 | 8 ++++++--
>   drivers/gpu/drm/amd/include/amd_shared.h                | 1 +
>   drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 5 +++++
>   3 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 2fd3a80bb034..ca3dce6d463e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -131,8 +131,12 @@ uint amdgpu_pg_mask = 0xffffffff;
>   uint amdgpu_sdma_phase_quantum = 32;
>   char *amdgpu_disable_cu = NULL;
>   char *amdgpu_virtual_display = NULL;
> -/* OverDrive(bit 14) disabled by default*/
> -uint amdgpu_pp_feature_mask = 0xffffbfff;
> +
> +/*
> + * OverDrive(bit 14) disabled by default
> + * GFX DCS(bit 19) disabled by default
> + */
> +uint amdgpu_pp_feature_mask = 0xfff7bfff;
>   uint amdgpu_force_long_training;
>   int amdgpu_job_hang_limit;
>   int amdgpu_lbpw = -1;
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
> index 9676016a37ce..43ed6291b2b8 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -213,6 +213,7 @@ enum PP_FEATURE_MASK {
>   	PP_ACG_MASK = 0x10000,
>   	PP_STUTTER_MODE = 0x20000,
>   	PP_AVFS_MASK = 0x40000,
> +	PP_GFX_DCS_MASK = 0x80000,
>   };
>   
>   enum DC_FEATURE_MASK {
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index cf59f2218b7e..fd090d057d26 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -261,6 +261,11 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
>   		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
>   	}
>   
> +	if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
> +	    (adev->asic_type > CHIP_SIENNA_CICHLID) &&
> +	    !(adev->flags & AMD_IS_APU))
> +		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> +
>   	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
>   		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>   					| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)