[PATCH 1/2] drm/amdgpu: Set GTT_USWC flag to enable freesync

Shashank Sharma shashank.sharma at amd.com
Sat Feb 13 16:37:24 UTC 2021

This patch sets 'AMDGPU_GEM_CREATE_CPU_GTT_USWC' as input
parameter flag, during object creation of an imported DMA

In absence of this flag:
1. Function amdgpu_display_supported_domains() doesn't add
   AMDGPU_GEM_DOMAIN_GTT as supported domain.
2. Due to which, Function amdgpu_display_user_framebuffer_create()
   refuses to create framebuffer for imported DMA buffers.
3. Due to which, AddFB() IOCTL fails.
4. Due to which, amdgpu_present_check_flip() check fails in DDX
5. Due to which DDX driver doesn't allow flips (goes to blitting)
6. Due to which setting Freesync/VRR property fails for PRIME buffers.

So, this patch finally enables Freesync with PRIME buffer offloading.

Cc: Koenig Christian <christian.koenig at amd.com>
Cc: Deucher Alexander <alexander.deucher at amd.com>
Signed-off-by: Shashank Sharma <shashank.sharma at amd.com>
 drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index 47e0b48dc26f..db62f3c9d6a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -448,8 +448,8 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
 	bp.resv = resv;
 	dma_resv_lock(resv, NULL);
 	ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
-			0, ttm_bo_type_sg, resv, &gobj);
+			ttm_bo_type_sg, resv, &gobj);
 	if (ret)
 		goto error;

More information about the amd-gfx mailing list