[PATCH 2/2] drm/amd/pm: optimize the link width/speed retrieving

[Quan, Evan]

[AMD Official Use Only - Internal Distribution Only]

PMFW of Arcturus does not expose us those information.
So, we have to stick to current implementation(smu_v11_0_get_current_pcie_link_width/speed) for Arcturus.

Regards
Evan
-----Original Message-----
From: Alex Deucher <alexdeucher at gmail.com> 
Sent: Tuesday, February 23, 2021 5:48 AM
To: Quan, Evan <Evan.Quan at amd.com>
Cc: amd-gfx list <amd-gfx at lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: Re: [PATCH 2/2] drm/amd/pm: optimize the link width/speed retrieving

On Sun, Feb 21, 2021 at 11:04 PM Evan Quan <evan.quan at amd.com> wrote:
>
> By using the information provided by PMFW when available.
>
> Change-Id: I1afec4cd07ac9608861ee07c449e320e3f36a932
> Signed-off-by: Evan Quan <evan.quan at amd.com>

What about arcturus?
Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 17 ++++++++++----
>  .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 22 +++++++++++++++----
>  2 files changed, 31 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 29e04f33f276..7fe2876c99fe 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -72,6 +72,8 @@
>
>  #define SMU_11_0_GFX_BUSY_THRESHOLD 15
>
> +static uint16_t link_speed[] = {25, 50, 80, 160};
> +
>  static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
>         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
>         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
> @@ -2391,10 +2393,17 @@ static ssize_t navi10_get_gpu_metrics(struct 
> smu_context *smu,
>
>         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
>
> -       gpu_metrics->pcie_link_width =
> -                       smu_v11_0_get_current_pcie_link_width(smu);
> -       gpu_metrics->pcie_link_speed =
> -                       smu_v11_0_get_current_pcie_link_speed(smu);
> +       if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
> +             ((adev->asic_type == CHIP_NAVI12) && smu_version > 0x00341C00) ||
> +             ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00)) {
> +               gpu_metrics->pcie_link_width = (uint16_t)metrics.PcieWidth;
> +               gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
> +       } else {
> +               gpu_metrics->pcie_link_width =
> +                               smu_v11_0_get_current_pcie_link_width(smu);
> +               gpu_metrics->pcie_link_speed =
> +                               smu_v11_0_get_current_pcie_link_speed(smu);
> +       }
>
>         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index e74299da1739..6fd95764c952 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -73,6 +73,8 @@
>
>  #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
>
> +static uint16_t link_speed[] = {25, 50, 80, 160};
> +
>  static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
>         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
>         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
> @@ -3124,6 +3126,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
>         SmuMetricsExternal_t metrics_external;
>         SmuMetrics_t *metrics =
>                 &(metrics_external.SmuMetrics);
> +       struct amdgpu_device *adev = smu->adev;
> +       uint32_t smu_version;
>         int ret = 0;
>
>         ret = smu_cmn_get_metrics_table(smu, @@ -3170,10 +3174,20 @@ 
> static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
>
>         gpu_metrics->current_fan_speed = metrics->CurrFanSpeed;
>
> -       gpu_metrics->pcie_link_width =
> -                       smu_v11_0_get_current_pcie_link_width(smu);
> -       gpu_metrics->pcie_link_speed =
> -                       smu_v11_0_get_current_pcie_link_speed(smu);
> +       ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
> +       if (ret)
> +               return ret;
> +
> +       if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu_version > 0x003A1E00) ||
> +             ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu_version > 0x00410400)) {
> +               gpu_metrics->pcie_link_width = (uint16_t)metrics->PcieWidth;
> +               gpu_metrics->pcie_link_speed = link_speed[metrics->PcieRate];
> +       } else {
> +               gpu_metrics->pcie_link_width =
> +                               smu_v11_0_get_current_pcie_link_width(smu);
> +               gpu_metrics->pcie_link_speed =
> +                               smu_v11_0_get_current_pcie_link_speed(smu);
> +       }
>
>         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
>
> --
> 2.29.0
>
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