[PATCH 094/159] drm/amdgpu: set snoop bit in pde/pte entries for Aldebaran A+A
Alex Deucher
alexander.deucher at amd.com
Wed Feb 24 22:17:54 UTC 2021
From: Eric Huang <jinhuieric.huang at amd.com>
Page tables in vram mapping to cpu is changed from uncached to
cached in A+A, the snoop bit in VM_CONTEXTx_PAGE_TABLE_BASE_ADDR/
PDE0s/PDE1s/PDE2s/PTE.TFs has to be set so gpuvm walker snoop
page table data out of CPU cache.
Signed-off-by: Eric Huang <jinhuieric.huang at amd.com>
Reviewed-by: Oak Zeng <Oak.Zeng at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 95d9ed411520..3a2a922c6c1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1538,6 +1538,9 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
flags |= AMDGPU_PTE_SNOOPED;
}
+ if (mem && mem->placement & TTM_PL_FLAG_CACHED)
+ flags |= AMDGPU_PTE_SNOOPED;
+
return flags;
}
--
2.29.2
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