[PATCH 2/2] drm/amd/amdgpu: Use IP discovery data to determine VCN enablement instead of MMSCH

[Leo Liu]

On 2021-01-05 5:54 p.m., Bokun Zhang wrote:
> In the past, we use MMSCH to determine whether a VCN is enabled or not.
> This is not reliable since after a FLR, MMSCH may report junk data.
>
> It is better to use IP discovery data.
>
> Change-Id: I8b6c32c34017b20dcaebffdaa78bb07178e9d03c
> Signed-off-by: Bokun Zhang <Bokun.Zhang at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 73 +++++++++++++++++----------
>   1 file changed, 45 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index def583916294..02cac6e33219 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -27,6 +27,7 @@
>   #include "amdgpu_pm.h"
>   #include "soc15.h"
>   #include "soc15d.h"
> +#include "soc15_hw_ip.h"
>   #include "vcn_v2_0.h"
>   #include "mmsch_v3_0.h"
>   
> @@ -60,6 +61,17 @@ static int amdgpu_ucode_id_vcns[] = {
>   	AMDGPU_UCODE_ID_VCN1
>   };
>   
> +#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
> +#define VCN_BLOCK_DECODE_DISABLE_MASK 0x40
> +#define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0
> +
> +enum vcn_ring_type {
> +	VCN_ENCODE_RING,
> +	VCN_DECODE_RING,
> +	VCN_UNIFIED_RING,
> +};
> +
> +static bool vcn_v3_0_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance);
>   static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
>   static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>   static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
> @@ -311,18 +323,26 @@ static int vcn_v3_0_hw_init(void *handle)
>   				continue;
>   
>   			ring = &adev->vcn.inst[i].ring_dec;
> -			if (ring->sched.ready) {
> +			if (vcn_v3_0_is_disabled_vcn(adev, VCN_DECODE_RING, i)) {
Since this is for SRIOV path only, and this doesn't apply to bare-metal, 
so please rename the function to something like xxx_sriov instead.

Regards,

Leo


> +				ring->sched.ready = false;
> +				dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
> +			} else {
>   				ring->wptr = 0;
>   				ring->wptr_old = 0;
>   				vcn_v3_0_dec_ring_set_wptr(ring);
> +				ring->sched.ready = true;
>   			}
>   
>   			for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
>   				ring = &adev->vcn.inst[i].ring_enc[j];
> -				if (ring->sched.ready) {
> +				if (vcn_v3_0_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
> +					ring->sched.ready = false;
> +					dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
> +				} else {
>   					ring->wptr = 0;
>   					ring->wptr_old = 0;
>   					vcn_v3_0_enc_ring_set_wptr(ring);
> +					ring->sched.ready = true;
>   				}
>   			}
>   		}
> @@ -1266,6 +1286,29 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
>   	return 0;
>   }
>   
> +static bool vcn_v3_0_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
> +{
> +	bool ret = false;
> +
> +	int major;
> +	int minor;
> +	int revision;
> +
> +	/* if cannot find IP data, then this VCN does not exist */
> +	if (amdgpu_discovery_get_ip_version(adev, VCN_HWID, vcn_instance, &major, &minor, &revision) != 0)
> +		return true;
> +
> +	if ((type == VCN_ENCODE_RING) && (revision & VCN_BLOCK_ENCODE_DISABLE_MASK)) {
> +		ret = true;
> +	} else if ((type == VCN_DECODE_RING) && (revision & VCN_BLOCK_DECODE_DISABLE_MASK)) {
> +		ret = true;
> +	} else if ((type == VCN_UNIFIED_RING) && (revision & VCN_BLOCK_QUEUE_DISABLE_MASK)) {
> +		ret = true;
> +	}
> +
> +	return ret;
> +}
> +
>   static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
>   {
>   	int i, j;
> @@ -1283,8 +1326,6 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
>   	uint32_t table_size;
>   	uint32_t size, size_dw;
>   
> -	bool is_vcn_ready;
> -
>   	struct mmsch_v3_0_cmd_direct_write
>   		direct_wt = { {0} };
>   	struct mmsch_v3_0_cmd_direct_read_modify_write
> @@ -1476,30 +1517,6 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
>   		}
>   	}
>   
> -	/* 6, check each VCN's init_status
> -	 * if it remains as 0, then this VCN is not assigned to current VF
> -	 * do not start ring for this VCN
> -	 */
> -	size = sizeof(struct mmsch_v3_0_init_header);
> -	table_loc = (uint32_t *)table->cpu_addr;
> -	memcpy(&header, (void *)table_loc, size);
> -
> -	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> -		if (adev->vcn.harvest_config & (1 << i))
> -			continue;
> -
> -		is_vcn_ready = (header.inst[i].init_status == 1);
> -		if (!is_vcn_ready)
> -			DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i);
> -
> -		ring = &adev->vcn.inst[i].ring_dec;
> -		ring->sched.ready = is_vcn_ready;
> -		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
> -			ring = &adev->vcn.inst[i].ring_enc[j];
> -			ring->sched.ready = is_vcn_ready;
> -		}
> -	}
> -
>   	return 0;
>   }
>