[PATCH 06/12] drm/amd/display: Set power gated default to true in seamless boot pipe

[Anson Jacob]

From: Lewis Huang <Lewis.Huang at amd.com>

[Why]
OS sequence will cause this flag didn't clear.
In seamless boot but without flip case. This flag didn't clear when
reset path mode because the plane_state is null
1. OS call setting with clone/extended
2. Reset path mode to remove edp.

[How]
Set power gated default to true in seamless boot pipe

Signed-off-by: Lewis Huang <Lewis.Huang at amd.com>
Reviewed-by: Martin Leung <Martin.Leung at amd.com>
Acked-by: Anson Jacob <Anson.Jacob at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7a30d1d9b535..2f315a47b765 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1224,6 +1224,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 			// signals when OTG blanked. This is to prevent pipe from
 			// requesting data while in PSR.
 			tg->funcs->tg_init(tg);
+			hubp->power_gated = true;
 			continue;
 		}
 
-- 
2.25.1