[RFC 2/7] drm/amd/display: Moves dcn30_set_mcif_arb_params to FPU folder
Rodrigo Siqueira
Rodrigo.Siqueira at amd.com
Mon Jan 25 13:43:08 UTC 2021
The function dcn30_set_mcif_arb_params uses some double-precision
operation; for this reason, this commit moves this function to the
directory fpu_operation, where all FPU operations should be centralized.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 81 +-----------------
.../drm/amd/display/dc/dcn30/dcn30_resource.h | 11 ---
.../amd/display/dc/dcn301/dcn301_resource.c | 2 +-
.../amd/display/dc/dcn302/dcn302_resource.c | 2 +-
.../display/dc/fpu_operation/dcn3x_commons.c | 84 +++++++++++++++++++
.../display/dc/fpu_operation/dcn3x_commons.h | 3 +
6 files changed, 90 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 02e3107f04ee..b82d616f8a21 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1471,85 +1471,6 @@ int dcn30_populate_dml_pipes_from_context(
return pipe_cnt;
}
-unsigned int dcn30_calc_max_scaled_time(
- unsigned int time_per_pixel,
- enum mmhubbub_wbif_mode mode,
- unsigned int urgent_watermark)
-{
- unsigned int time_per_byte = 0;
- unsigned int total_free_entry = 0xb40;
- unsigned int buf_lh_capability;
- unsigned int max_scaled_time;
-
- if (mode == PACKED_444) /* packed mode 32 bpp */
- time_per_byte = time_per_pixel/4;
- else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
- time_per_byte = time_per_pixel/8;
-
- if (time_per_byte == 0)
- time_per_byte = 1;
-
- buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
- max_scaled_time = buf_lh_capability - urgent_watermark;
- return max_scaled_time;
-}
-
-void dcn30_set_mcif_arb_params(
- struct dc *dc,
- struct dc_state *context,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt)
-{
- enum mmhubbub_wbif_mode wbif_mode;
- struct display_mode_lib *dml = &context->bw_ctx.dml;
- struct mcif_arb_params *wb_arb_params;
- int i, j, k, dwb_pipe;
-
- /* Writeback MCIF_WB arbitration parameters */
- dwb_pipe = 0;
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
-
- if (!context->res_ctx.pipe_ctx[i].stream)
- continue;
-
- for (j = 0; j < MAX_DWB_PIPES; j++) {
- struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
-
- if (writeback_info->wb_enabled == false)
- continue;
-
- //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
- wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
-
- if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
- writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
- wbif_mode = PACKED_444_FP16;
- else
- wbif_mode = PACKED_444;
-
- for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
- wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;
- wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
- }
- wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
- wb_arb_params->slice_lines = 32;
- wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
- wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
- wbif_mode,
- wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
- wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
-
- dwb_pipe++;
-
- if (dwb_pipe >= MAX_DWB_PIPES)
- return;
- }
- if (dwb_pipe >= MAX_DWB_PIPES)
- return;
- }
-
-}
-
static struct dc_cap_funcs cap_funcs = {
.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
};
@@ -2402,7 +2323,7 @@ static const struct resource_funcs dcn30_res_pool_funcs = {
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
.populate_dml_writeback_from_context = dcn3x_populate_dml_writeback_from_context,
- .set_mcif_arb_params = dcn30_set_mcif_arb_params,
+ .set_mcif_arb_params = dcn3x_set_mcif_arb_params,
.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
index b91e2856097f..42960574cce9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
@@ -42,17 +42,6 @@ struct resource_pool *dcn30_create_resource_pool(
const struct dc_init_data *init_data,
struct dc *dc);
-void dcn30_set_mcif_arb_params(
- struct dc *dc,
- struct dc_state *context,
- display_e2e_pipe_params_st *pipes,
- int pipe_cnt);
-
-unsigned int dcn30_calc_max_scaled_time(
- unsigned int time_per_pixel,
- enum mmhubbub_wbif_mode mode,
- unsigned int urgent_watermark);
-
bool dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
bool fast_validate);
void dcn30_calculate_wm_and_dlg(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index e57f365aef95..8369b009a853 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1632,7 +1632,7 @@ static struct resource_funcs dcn301_res_pool_funcs = {
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
.populate_dml_writeback_from_context = dcn3x_populate_dml_writeback_from_context,
- .set_mcif_arb_params = dcn30_set_mcif_arb_params,
+ .set_mcif_arb_params = dcn3x_set_mcif_arb_params,
.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index c0f4a6d10cb6..0554a3dd3214 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1242,7 +1242,7 @@ static struct resource_funcs dcn302_res_pool_funcs = {
.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
.populate_dml_writeback_from_context = dcn3x_populate_dml_writeback_from_context,
- .set_mcif_arb_params = dcn30_set_mcif_arb_params,
+ .set_mcif_arb_params = dcn3x_set_mcif_arb_params,
.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
diff --git a/drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.c b/drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.c
index 767ca59551c1..707f782127a7 100644
--- a/drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.c
+++ b/drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.c
@@ -137,6 +137,90 @@ static void _dcn3x_populate_dml_writeback_from_context(struct dc *dc,
}
+static unsigned int dcn3x_calc_max_scaled_time(unsigned int time_per_pixel,
+ enum mmhubbub_wbif_mode mode, unsigned int urgent_watermark)
+{
+ unsigned int time_per_byte = 0;
+ unsigned int total_free_entry = 0xb40;
+ unsigned int buf_lh_capability;
+ unsigned int max_scaled_time;
+
+ if (mode == PACKED_444) /* packed mode 32 bpp */
+ time_per_byte = time_per_pixel/4;
+ else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
+ time_per_byte = time_per_pixel/8;
+
+ if (time_per_byte == 0)
+ time_per_byte = 1;
+
+ buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
+ max_scaled_time = buf_lh_capability - urgent_watermark;
+ return max_scaled_time;
+}
+
+static void _dcn3x_set_mcif_arb_params(struct dc *dc, struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt)
+{
+ enum mmhubbub_wbif_mode wbif_mode;
+ struct display_mode_lib *dml = &context->bw_ctx.dml;
+ struct mcif_arb_params *wb_arb_params;
+ int i, j, k, dwb_pipe;
+
+ /* Writeback MCIF_WB arbitration parameters */
+ dwb_pipe = 0;
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+
+ if (!context->res_ctx.pipe_ctx[i].stream)
+ continue;
+
+ for (j = 0; j < MAX_DWB_PIPES; j++) {
+ struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
+
+ if (writeback_info->wb_enabled == false)
+ continue;
+
+ //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
+ wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
+
+ if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
+ writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
+ wbif_mode = PACKED_444_FP16;
+ else
+ wbif_mode = PACKED_444;
+
+ for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
+ wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;
+ wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
+ }
+ wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
+ wb_arb_params->slice_lines = 32;
+ wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
+ wb_arb_params->max_scaled_time = dcn3x_calc_max_scaled_time(wb_arb_params->time_per_pixel,
+ wbif_mode,
+ wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
+ wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
+
+ dwb_pipe++;
+
+ if (dwb_pipe >= MAX_DWB_PIPES)
+ return;
+ }
+ if (dwb_pipe >= MAX_DWB_PIPES)
+ return;
+ }
+
+}
+
+void dcn3x_set_mcif_arb_params(struct dc *dc, struct dc_state *context,
+ display_e2e_pipe_params_st *pipes,
+ int pipe_cnt)
+{
+ DC_FP_START();
+ _dcn3x_set_mcif_arb_params(dc, context, pipes, pipe_cnt);
+ DC_FP_END();
+}
+
void dcn3x_populate_dml_writeback_from_context(struct dc *dc,
struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
{
diff --git a/drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.h b/drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.h
index c3d6297d3585..b3b6d8a66c28 100644
--- a/drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.h
+++ b/drivers/gpu/drm/amd/display/dc/fpu_operation/dcn3x_commons.h
@@ -29,4 +29,7 @@
void dcn3x_populate_dml_writeback_from_context(struct dc *dc,
struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
+void dcn3x_set_mcif_arb_params(struct dc *dc, struct dc_state *context,
+ display_e2e_pipe_params_st *pipes, int pipe_cnt);
+
#endif /* _DCN3X_COMMONS_H_ */
--
2.25.1
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