[PATCH 2/4] drm/amdgpu: add video decode/encode cap tables and asic callbacks
Alex Deucher
alexdeucher at gmail.com
Wed Jan 27 05:32:29 UTC 2021
For each asic family. Will be used to populate tables
for the new INFO ioctl query.
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 70 ++++++++++
drivers/gpu/drm/amd/amdgpu/nv.c | 162 ++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/si.c | 104 +++++++++++++++
drivers/gpu/drm/amd/amdgpu/soc15.c | 208 +++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/vi.c | 175 ++++++++++++++++++++++++
5 files changed, 719 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 13737b317f7c..54c85297dba8 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -70,6 +70,75 @@
#include "amdgpu_amdkfd.h"
#include "dce_virtual.h"
+static const struct amdgpu_video_codec_info cik_video_codecs_encode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 2048,
+ .max_height = 1152,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs cik_video_codecs_encode =
+{
+ .codec_count = ARRAY_SIZE(cik_video_codecs_encode_array),
+ .codec_array = cik_video_codecs_encode_array,
+};
+
+static const struct amdgpu_video_codec_info cik_video_codecs_decode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG2,
+ .max_width = 2048,
+ .max_height = 1152,
+ .max_level = 3,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4,
+ .max_width = 2048,
+ .max_height = 1152,
+ .max_level = 5,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 2048,
+ .max_height = 1152,
+ .max_level = 41,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VC1,
+ .max_width = 2048,
+ .max_height = 1152,
+ .max_level = 4,
+ },
+};
+
+static const struct amdgpu_video_codecs cik_video_codecs_decode =
+{
+ .codec_count = ARRAY_SIZE(cik_video_codecs_decode_array),
+ .codec_array = cik_video_codecs_decode_array,
+};
+
+static int cik_query_video_codecs(struct amdgpu_device *adev, bool encode,
+ const struct amdgpu_video_codecs **codecs)
+{
+ switch (adev->asic_type) {
+ case CHIP_BONAIRE:
+ case CHIP_HAWAII:
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+ if (encode)
+ *codecs = &cik_video_codecs_encode;
+ else
+ *codecs = &cik_video_codecs_decode;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
/*
* Indirect registers accessor
*/
@@ -1944,6 +2013,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
.get_pcie_replay_count = &cik_get_pcie_replay_count,
.supports_baco = &cik_asic_supports_baco,
.pre_asic_init = &cik_pre_asic_init,
+ .query_video_codecs = &cik_query_video_codecs,
};
static int cik_common_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 66279f0c6808..eabc11bc33aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -64,6 +64,167 @@
static const struct amd_ip_funcs nv_common_ip_funcs;
+/* Navi */
+static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 4096,
+ .max_height = 2304,
+ .max_level = 0,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_HEVC,
+ .max_width = 4096,
+ .max_height = 2304,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs nv_video_codecs_encode =
+{
+ .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
+ .codec_array = nv_video_codecs_encode_array,
+};
+
+/* Navi1x */
+static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG2,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 3,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 5,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 52,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VC1,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 4,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_HEVC,
+ .max_width = 8192,
+ .max_height = 4352,
+ .max_level = 186,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_JPEG,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 0,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VP9,
+ .max_width = 8192,
+ .max_height = 4352,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs nv_video_codecs_decode =
+{
+ .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
+ .codec_array = nv_video_codecs_decode_array,
+};
+
+/* Sienna Cichlid */
+static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG2,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 3,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 5,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 52,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VC1,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 4,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_HEVC,
+ .max_width = 8192,
+ .max_height = 4352,
+ .max_level = 186,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_JPEG,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 0,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VP9,
+ .max_width = 8192,
+ .max_height = 4352,
+ .max_level = 0,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_AV1,
+ .max_width = 8192,
+ .max_height = 4352,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs sc_video_codecs_decode =
+{
+ .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
+ .codec_array = sc_video_codecs_decode_array,
+};
+
+static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
+ const struct amdgpu_video_codecs **codecs)
+{
+ switch (adev->asic_type) {
+ case CHIP_SIENNA_CICHLID:
+ case CHIP_NAVY_FLOUNDER:
+ case CHIP_DIMGREY_CAVEFISH:
+ case CHIP_VANGOGH:
+ if (encode)
+ *codecs = &nv_video_codecs_encode;
+ else
+ *codecs = &sc_video_codecs_decode;
+ return 0;
+ case CHIP_NAVI10:
+ case CHIP_NAVI14:
+ case CHIP_NAVI12:
+ if (encode)
+ *codecs = &nv_video_codecs_encode;
+ else
+ *codecs = &nv_video_codecs_decode;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
/*
* Indirect registers accessor
*/
@@ -825,6 +986,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
.supports_baco = &nv_asic_supports_baco,
.pre_asic_init = &nv_pre_asic_init,
.update_umd_stable_pstate = &nv_update_umd_stable_pstate,
+ .query_video_codecs = &nv_query_video_codecs,
};
static int nv_common_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 3cf0589bfea5..242ddd9b5d75 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -905,6 +905,109 @@ static const u32 hainan_mgcg_cgcg_init[] =
0x3630, 0xfffffff0, 0x00000100,
};
+/* XXX: update when we support VCE */
+#if 0
+/* tahiti, pitcarin, verde */
+static const struct amdgpu_video_codec_info tahiti_video_codecs_encode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 2048,
+ .max_height = 1152,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs tahiti_video_codecs_encode =
+{
+ .codec_count = ARRAY_SIZE(tahiti_video_codecs_encode_array),
+ .codec_array = tahiti_video_codecs_encode_array,
+};
+#else
+static const struct amdgpu_video_codecs tahiti_video_codecs_encode =
+{
+ .codec_count = 0,
+ .codec_array = NULL,
+};
+#endif
+/* oland and hainan don't support encode */
+static const struct amdgpu_video_codecs hainan_video_codecs_encode =
+{
+ .codec_count = 0,
+ .codec_array = NULL,
+};
+
+/* tahiti, pitcarin, verde, oland */
+static const struct amdgpu_video_codec_info tahiti_video_codecs_decode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG2,
+ .max_width = 2048,
+ .max_height = 1152,
+ .max_level = 3,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4,
+ .max_width = 2048,
+ .max_height = 1152,
+ .max_level = 5,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 2048,
+ .max_height = 1152,
+ .max_level = 41,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VC1,
+ .max_width = 2048,
+ .max_height = 1152,
+ .max_level = 4,
+ },
+};
+
+static const struct amdgpu_video_codecs tahiti_video_codecs_decode =
+{
+ .codec_count = ARRAY_SIZE(tahiti_video_codecs_decode_array),
+ .codec_array = tahiti_video_codecs_decode_array,
+};
+
+/* hainan doesn't support decode */
+static const struct amdgpu_video_codecs hainan_video_codecs_decode =
+{
+ .codec_count = 0,
+ .codec_array = NULL,
+};
+
+static int si_query_video_codecs(struct amdgpu_device *adev, bool encode,
+ const struct amdgpu_video_codecs **codecs)
+{
+ switch (adev->asic_type) {
+ case CHIP_VERDE:
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ if (encode)
+ *codecs = &tahiti_video_codecs_encode;
+ else
+ *codecs = &tahiti_video_codecs_decode;
+ return 0;
+ case CHIP_OLAND:
+ if (encode)
+ *codecs = &hainan_video_codecs_encode;
+ else
+ *codecs = &tahiti_video_codecs_decode;
+ return 0;
+ case CHIP_HAINAN:
+ if (encode)
+ *codecs = &hainan_video_codecs_encode;
+ else
+ *codecs = &hainan_video_codecs_decode;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
{
unsigned long flags;
@@ -1897,6 +2000,7 @@ static const struct amdgpu_asic_funcs si_asic_funcs =
.get_pcie_replay_count = &si_get_pcie_replay_count,
.supports_baco = &si_asic_supports_baco,
.pre_asic_init = &si_pre_asic_init,
+ .query_video_codecs = &si_query_video_codecs,
};
static uint32_t si_get_rev_id(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 2396be16c28e..3c8b595fb39a 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -83,6 +83,212 @@
#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
+/* Vega, Raven, Arcturus */
+static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 4096,
+ .max_height = 2304,
+ .max_level = 0,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_HEVC,
+ .max_width = 4096,
+ .max_height = 2304,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs vega_video_codecs_encode =
+{
+ .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
+ .codec_array = vega_video_codecs_encode_array,
+};
+
+/* Vega */
+static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG2,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 3,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 5,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 52,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VC1,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 4,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_HEVC,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 186,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_JPEG,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs vega_video_codecs_decode =
+{
+ .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
+ .codec_array = vega_video_codecs_decode_array,
+};
+
+/* Raven */
+static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG2,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 3,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 5,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 52,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VC1,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 4,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_HEVC,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 186,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_JPEG,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 0,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VP9,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs rv_video_codecs_decode =
+{
+ .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
+ .codec_array = rv_video_codecs_decode_array,
+};
+
+/* Renoir, Arcturus */
+static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG2,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 3,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 5,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 52,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VC1,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 4,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_HEVC,
+ .max_width = 8192,
+ .max_height = 4352,
+ .max_level = 186,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_JPEG,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 0,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VP9,
+ .max_width = 8192,
+ .max_height = 4352,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs rn_video_codecs_decode =
+{
+ .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
+ .codec_array = rn_video_codecs_decode_array,
+};
+
+static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
+ const struct amdgpu_video_codecs **codecs)
+{
+ switch (adev->asic_type) {
+ case CHIP_VEGA20:
+ case CHIP_VEGA10:
+ case CHIP_VEGA12:
+ if (encode)
+ *codecs = &vega_video_codecs_encode;
+ else
+ *codecs = &vega_video_codecs_decode;
+ return 0;
+ case CHIP_RAVEN:
+ if (encode)
+ *codecs = &vega_video_codecs_encode;
+ else
+ *codecs = &rv_video_codecs_decode;
+ return 0;
+ case CHIP_ARCTURUS:
+ case CHIP_RENOIR:
+ if (encode)
+ *codecs = &vega_video_codecs_encode;
+ else
+ *codecs = &rn_video_codecs_decode;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
/*
* Indirect registers accessor
*/
@@ -988,6 +1194,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
.get_pcie_replay_count = &soc15_get_pcie_replay_count,
.supports_baco = &soc15_supports_baco,
.pre_asic_init = &soc15_pre_asic_init,
+ .query_video_codecs = &soc15_query_video_codecs,
};
static const struct amdgpu_asic_funcs vega20_asic_funcs =
@@ -1009,6 +1216,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
.get_pcie_replay_count = &soc15_get_pcie_replay_count,
.supports_baco = &soc15_supports_baco,
.pre_asic_init = &soc15_pre_asic_init,
+ .query_video_codecs = &soc15_query_video_codecs,
};
static int soc15_common_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index d56b474b3a21..ed9de0950849 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -79,6 +79,180 @@
#include "mxgpu_vi.h"
#include "amdgpu_dm.h"
+/* Topaz */
+static const struct amdgpu_video_codecs topaz_video_codecs_encode =
+{
+ .codec_count = 0,
+ .codec_array = NULL,
+};
+
+/* Tonga, CZ, ST, Fiji */
+static const struct amdgpu_video_codec_info tonga_video_codecs_encode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 4096,
+ .max_height = 2304,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs tonga_video_codecs_encode =
+{
+ .codec_count = ARRAY_SIZE(tonga_video_codecs_encode_array),
+ .codec_array = tonga_video_codecs_encode_array,
+};
+
+/* Polaris */
+static const struct amdgpu_video_codec_info polaris_video_codecs_encode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 4096,
+ .max_height = 2304,
+ .max_level = 0,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_HEVC,
+ .max_width = 4096,
+ .max_height = 2304,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs polaris_video_codecs_encode =
+{
+ .codec_count = ARRAY_SIZE(polaris_video_codecs_encode_array),
+ .codec_array = polaris_video_codecs_encode_array,
+};
+
+/* Topaz */
+static const struct amdgpu_video_codecs topaz_video_codecs_decode =
+{
+ .codec_count = 0,
+ .codec_array = NULL,
+};
+
+/* Tonga */
+static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG2,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 3,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 5,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 52,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VC1,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 4,
+ },
+};
+
+static const struct amdgpu_video_codecs tonga_video_codecs_decode =
+{
+ .codec_count = ARRAY_SIZE(tonga_video_codecs_decode_array),
+ .codec_array = tonga_video_codecs_decode_array,
+};
+
+/* CZ, ST, Fiji, Polaris */
+static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] =
+{
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG2,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 3,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 5,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_MPEG4_AVC,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 52,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_VC1,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 4,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_HEVC,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 186,
+ },
+ {
+ .codec_type = AMDGPU_VIDEO_CODEC_TYPE_JPEG,
+ .max_width = 4096,
+ .max_height = 4096,
+ .max_level = 0,
+ },
+};
+
+static const struct amdgpu_video_codecs cz_video_codecs_decode =
+{
+ .codec_count = ARRAY_SIZE(cz_video_codecs_decode_array),
+ .codec_array = cz_video_codecs_decode_array,
+};
+
+static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode,
+ const struct amdgpu_video_codecs **codecs)
+{
+ switch (adev->asic_type) {
+ case CHIP_TOPAZ:
+ if (encode)
+ *codecs = &topaz_video_codecs_encode;
+ else
+ *codecs = &topaz_video_codecs_decode;
+ return 0;
+ case CHIP_TONGA:
+ if (encode)
+ *codecs = &tonga_video_codecs_encode;
+ else
+ *codecs = &tonga_video_codecs_decode;
+ return 0;
+ case CHIP_POLARIS10:
+ case CHIP_POLARIS11:
+ case CHIP_POLARIS12:
+ case CHIP_VEGAM:
+ if (encode)
+ *codecs = &polaris_video_codecs_encode;
+ else
+ *codecs = &cz_video_codecs_decode;
+ return 0;
+ case CHIP_FIJI:
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+ if (encode)
+ *codecs = &tonga_video_codecs_encode;
+ else
+ *codecs = &cz_video_codecs_decode;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
/*
* Indirect registers accessor
*/
@@ -1093,6 +1267,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
.get_pcie_replay_count = &vi_get_pcie_replay_count,
.supports_baco = &vi_asic_supports_baco,
.pre_asic_init = &vi_pre_asic_init,
+ .query_video_codecs = &vi_query_video_codecs,
};
#define CZ_REV_BRISTOL(rev) \
--
2.29.2
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