[PATCH] drm/amdgpu: return error type when programing registers fails

[Roy Sun]

Signed-off-by: Roy Sun <Roy.Sun at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bc4347a72301..af92c6f63dee 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -56,6 +56,15 @@
 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	1
 #define GFX10_MEC_HPD_SIZE	2048
 
+#define INTERFACE_NOT_ENABLED_FLAG	0x4000000
+#define WRONG_OPERATION_TYPE_FLAG	0x2000000
+#define NOT_IN_RANGE_FLAG	0x1000000
+
+#define RLCG_UNKNOWN_TYPE	0
+#define RLCG_INTERFACE_NOT_ENABLED	1
+#define RLCG_WRONG_OPERATION_TYPE	2
+#define RLCG_NOT_IN_RANGE	3
+
 #define F32_CE_PROGRAM_RAM_SIZE		65536
 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
 
@@ -1533,8 +1542,17 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
 			udelay(10);
 		}
 
-		if (i >= retries)
-			pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
+		if (i >= retries) {
+			int error_type = RLCG_UNKNOWN_TYPE;
+
+			if (tmp & INTERFACE_NOT_ENABLED_FLAG && !error_type)
+				error_type = RLCG_INTERFACE_NOT_ENABLED;
+			if (tmp & WRONG_OPERATION_TYPE_FLAG && !error_type)
+				error_type = RLCG_WRONG_OPERATION_TYPE;
+			if (tmp & NOT_IN_RANGE_FLAG && !error_type)
+				error_type = RLCG_NOT_IN_RANGE;
+			pr_err("timeout: rlcg program reg:0x%05x failed! Error type: %d.\n", offset, error_type);
+		}
 	}
 
 	ret = readl(scratch_reg0);
-- 
2.32.0