[PATCH] drm/amdgpu: Add error message when programing registers fails

[Roy Sun]

Signed-off-by: Roy Sun <Roy.Sun at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bc4347a72301..a7e03bba72b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -56,6 +56,10 @@
 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	1
 #define GFX10_MEC_HPD_SIZE	2048
 
+#define INTERFACE_NOT_ENABLED_FLAG	0x4000000
+#define WRONG_OPERATION_TYPE_FLAG	0x2000000
+#define NOT_IN_RANGE_FLAG	0x1000000
+
 #define F32_CE_PROGRAM_RAM_SIZE		65536
 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
 
@@ -1523,9 +1527,9 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
 		writel(v, scratch_reg0);
 		writel(offset | flag, scratch_reg1);
 		writel(1, spare_int);
-		for (i = 0; i < retries; i++) {
-			u32 tmp;
+		u32 tmp;
 
+		for (i = 0; i < retries; i++) {
 			tmp = readl(scratch_reg1);
 			if (!(tmp & flag))
 				break;
@@ -1533,8 +1537,18 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
 			udelay(10);
 		}
 
-		if (i >= retries)
-			pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
+		if (i >= retries) {
+			pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
+			if (amdgpu_sriov_reg_indirect_mmhub(adev) ||
+					amdgpu_sriov_reg_indirect_gc(adev)) {
+				if (tmp & INTERFACE_NOT_ENABLED_FLAG)
+					pr_err("The interface is not eabled!\n");
+				if (tmp & WRONG_OPERATION_TYPE_FLAG)
+					pr_err("Wrong operation type!\n");
+				if (tmp & NOT_IN_RANGE_FLAG)
+					pr_err("The register is not in range!\n");
+			}
+		}
 	}
 
 	ret = readl(scratch_reg0);
-- 
2.32.0