[PATCH 00/30] DC Patches June, 7, 2021

Wheeler, Daniel Daniel.Wheeler at amd.com
Tue Jun 8 14:00:15 UTC 2021


[Public]

Hi all,
 
This week this patchset was tested on the following systems:

HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)

AMD Ryzen 9 5900H, with the following display types: eDP 1080p 60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
 
Sapphire Pulse RX5700XT with the following display types:
4k 60hz  (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
 
Reference AMD RX6800 with the following display types:
4k 60hz  (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
 
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems.

 
Tested-by: Daniel Wheeler <daniel.wheeler at amd.com>

 
Thank you,
 
Dan Wheeler
Technologist  |  AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
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-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Stylon Wang
Sent: June 7, 2021 12:47 PM
To: amd-gfx at lists.freedesktop.org
Cc: Wang, Chao-kai (Stylon) <Stylon.Wang at amd.com>; Brol, Eryk <Eryk.Brol at amd.com>; Li, Sun peng (Leo) <Sunpeng.Li at amd.com>; Wentland, Harry <Harry.Wentland at amd.com>; Zhuo, Qingqing <Qingqing.Zhuo at amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira at amd.com>; Jacob, Anson <Anson.Jacob at amd.com>; Pillai, Aurabindo <Aurabindo.Pillai at amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha at amd.com>; R, Bindu <Bindu.R at amd.com>
Subject: [PATCH 00/30] DC Patches June, 7, 2021

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* DC v3.2.139
* FW v0.0.69
* Improvements across DP, eDP, DMUB, MPO, etc

--

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.68

Aric Cyr (4):
  drm/amd/display: Change default policy for MPO with multidisplay
  drm/amd/display: 3.2.138
  drm/amd/display: Fix crash during MPO + ODM combine mode recalculation
  drm/amd/display: 3.2.139

Dingchen (David) Zhang (1):
  drm/amd/display: force CP to DESIRED when removing display

Eric Bernstein (1):
  drm/amd/display: Updates for ODM Transition Test

Evgenii Krasnikov (1):
  drm/amd/display: add visual confirm colors to differentiate
    layer_index > 0

Fangzhi Zuo (1):
  drm/amd/display: Add debugfs entry for dsc passthrough

Ilya Bakoulin (1):
  drm/amd/display: Revert "Fix clock table filling logic"

Jake Wang (1):
  drm/amd/display: Trigger full update after DCC on/off

Jayendran Ramani (1):
  drm/amd/display: Return last used DRR VTOTAL from DC

Jimmy Kizito (2):
  drm/amd/display: Expand DP module equalization API.
  drm/amd/display: Support mappable encoders when transmitting training
    patterns.

JinZe.Xu (1):
  drm/amd/display: Control power gating by driver.

Meenakshikumar Somasundaram (1):
  drm/amd/display: Remove unused definition of DMUB SET_CONFIG

Mikita Lipski (2):
  drm/amd/display: Enabling PSR support for multiple panels
  drm/amd/display: Enable PSR Residency for multiple panels

Nikola Cornij (1):
  drm/amd/display: Fix DCN 3.01 DSCCLK validation

Po-Ting Chen (1):
  drm/amd/display: Add swizzle visual confirm mode

Roman Li (1):
  drm/amd/display: Update scaling settings on modeset

Roy Chan (1):
  drm/amd/display: Revert "Disconnect non-DP with no EDID"

Vladimir Stempen (1):
  drm/amd/display: Release MST resources on switch from MST to SST

Wenjing Liu (1):
  drm/amd/display: delay 100ms before restart after failing to read
    CP_IRQ

Wesley Chalmers (4):
  drm/amd/display: Add Interface to set FIFO ERRDET SW Override
  drm/amd/display: Add interface for ADD & DROP PIXEL Registers
  drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7
  drm/amd/display: Fix off-by-one error in DML

Wyatt Wood (2):
  drm/amd/display: Refactor visual confirm
  drm/amd/display: [FW Promotion] Release 0.0.69

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   3 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  50 ++++++-
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    |  15 +-
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |  22 ++-  .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |  78 ++++------
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  60 +++++++-
 .../drm/amd/display/dc/core/dc_hw_sequencer.c | 133 ++++++++++++++++++  drivers/gpu/drm/amd/display/dc/core/dc_link.c |  47 +++----  .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  24 ++--
 .../drm/amd/display/dc/core/dc_link_hwss.c    |  11 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   5 +
 drivers/gpu/drm/amd/display/dc/dc.h           |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |   4 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  41 ++++--  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  17 ++-
 .../display/dc/dce110/dce110_hw_sequencer.c   |  35 -----
 .../dc/dce110/dce110_timing_generator.c       |   1 +
 .../dc/dce120/dce120_timing_generator.c       |   1 +
 .../display/dc/dce80/dce80_timing_generator.c |   1 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 110 +++------------  .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  12 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |   4 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |   1 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   4 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c |  36 +++++  .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  76 +++++++++-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  47 +++----
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h    |   5 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  10 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   9 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c |   3 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   3 +-
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  37 ++---
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c |   3 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h |  17 ++-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |   3 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c |   1 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.h |   6 +-
 .../drm/amd/display/dc/dcn30/dcn30_resource.c |   2 +-
 .../drm/amd/display/dc/dcn301/dcn301_dccg.c   |   3 +
 .../drm/amd/display/dc/dcn301/dcn301_init.c   |   3 +-
 .../drm/amd/display/dc/dcn302/dcn302_hwseq.c  |  34 ++---
 .../amd/display/dc/dcn302/dcn302_resource.c   |   2 +-
 .../amd/display/dc/dcn303/dcn303_resource.c   |   2 +-
 .../dc/dml/dcn30/display_mode_vba_30.c        |  78 ++++------
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |   8 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |   6 +
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   |   3 +
 .../amd/display/dc/inc/hw/timing_generator.h  |   1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  17 +++
 .../amd/display/dc/inc/hw_sequencer_private.h |   5 -
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  96 +++++++++++--
 .../display/modules/hdcp/hdcp2_transition.c   |   2 +-
 59 files changed, 788 insertions(+), 426 deletions(-)

--
2.25.1

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