[PATCH] drm/amdgpu: PWRBRK sequence changes for Aldebaran

[Lazar, Lijo]

[AMD Official Use Only]

Reviewed-by: Lijo Lazar <lijo.lazar at amd.com>

-----Original Message-----
From: Ashish Pawar <ashpawar at amd.com> 
Sent: Thursday, June 10, 2021 12:18 AM
To: amd-gfx at lists.freedesktop.org
Cc: Lazar, Lijo <Lijo.Lazar at amd.com>; Quan, Evan <Evan.Quan at amd.com>; Pawar, Ashish <Ashish.Pawar at amd.com>
Subject: [PATCH] drm/amdgpu: PWRBRK sequence changes for Aldebaran

Modify power brake enablement sequence on Aldebaran

Signed-off-by: Ashish Pawar <ashpawar at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
index c0352dcc89be..1769c4cba2ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -782,11 +782,6 @@ void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev)
 	tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);
 	WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp);
 
-	WREG32_SOC15(GC, 0, regDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
-	tmp = 0;
-	tmp = REG_SET_FIELD(tmp, DIDT_SQ_THROTTLE_CTRL, PWRBRK_STALL_EN, 1);
-	WREG32_SOC15(GC, 0, regDIDT_IND_DATA, tmp);
-
 	WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
 	tmp = 0;
 	tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);
-- 
2.25.1