[PATCH 00/24] DC Patches June 10, 2021

Wheeler, Daniel Daniel.Wheeler at amd.com
Mon Jun 14 13:23:14 UTC 2021 

[Public]

Hi all,
 
This week this patchset was tested on the following systems:
 
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
 
AMD Ryzen 9 5900H, with the following display types: eDP 1080p 60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
 
Sapphire Pulse RX5700XT with the following display types:
4k 60hz  (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
 
Reference AMD RX6800 with the following display types:
4k 60hz  (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
 
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems.
 
 
Tested-by: Daniel Wheeler <daniel.wheeler at amd.com>
 
 
Thank you,
 
Dan Wheeler
Technologist  |  AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
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-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Anson Jacob
Sent: June 10, 2021 12:28 PM
To: amd-gfx at lists.freedesktop.org
Cc: Brol, Eryk <Eryk.Brol at amd.com>; Li, Sun peng (Leo) <Sunpeng.Li at amd.com>; Wentland, Harry <Harry.Wentland at amd.com>; Zhuo, Qingqing <Qingqing.Zhuo at amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira at amd.com>; Li, Roman <Roman.Li at amd.com>; Jacob, Anson <Anson.Jacob at amd.com>; Pillai, Aurabindo <Aurabindo.Pillai at amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha at amd.com>; R, Bindu <Bindu.R at amd.com>
Subject: [PATCH 00/24] DC Patches June 10, 2021

This DC patchset brings improvements in multiple areas. In summary, we have:
* LTTPR improvements
* Backlight improvements
* eDP hotplug detection

*** BLURB HERE ***

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.70

Aric Cyr (1):
  drm/amd/display: 3.2.140

Ashley Thomas (1):
  drm/amd/display: add DMUB registers to crash dump diagnostic data.

David Galiffi (1):
  drm/amd/display: Updated variable name.

Dmytro Laktyushkin (1):
  drm/amd/display: Remove unnecessary blank lines

Josip Pavic (1):
  drm/amd/display: tune backlight ramping profiles

Po-Ting Chen (1):
  drm/amd/display: Change swizzle visual confirm reference pipe

Roman Li (1):
  drm/amd/display: move psr dm interface to separate files

Wenjing Liu (1):
  drm/amd/display: dp mst detection code refactor

Wesley Chalmers (14):
  drm/amd/display: Read LTTPR caps first on hotplug
  drm/amd/display: Move LTTPR cap read into its own function
  drm/amd/display: Read LTTPR caps first on bootup
  drm/amd/display: Set LTTPR Transparent Mode after read link cap
  drm/amd/display: Always write repeater mode regardless of LTTPR
  drm/amd/display: Improve logic for is_lttpr_present
  drm/amd/display: Enforce DPCD Address ranges
  drm/amd/display: Rename constant
  drm/amd/display: 7 retries + 50 ms timeout on AUX DEFER
  drm/amd/display: Do not count I2C DEFERs with AUX DEFERs
  drm/amd/display: Partition DPCD address space and break up
    transactions
  drm/amd/display: Add interface to get Calibrated Avg Level from FIFO
  drm/amd/display: Cover edge-case when changing DISPCLK WDIVIDER
  drm/amd/display: Extend AUX timeout for DP initial reads

Yi-Ling Chen (1):
  drm/amd/display: add config option for eDP hotplug detection

 .../gpu/drm/amd/display/amdgpu_dm/Makefile    |   2 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 137 +----------  .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 166 +++++++++++++  .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h |  37 +++
 drivers/gpu/drm/amd/display/dc/Makefile       |   2 +-
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  |  68 +++++-
 .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h  |   3 +-
 .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c  |   4 +-
 .../drm/amd/display/dc/core/dc_hw_sequencer.c |  10 +-  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 167 ++++++--------  .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 170 +++++++-------
 .../drm/amd/display/dc/core/dc_link_dpcd.c    | 218 ++++++++++++++++++
 .../drm/amd/display/dc/core/dc_link_hwss.c    |  31 +--
 drivers/gpu/drm/amd/display/dc/dc.h           |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  | 100 +++++++-
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h  |   4 +
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  |  23 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   5 +
 .../display/dc/dcn10/dcn10_stream_encoder.h   |  24 ++
 .../display/dc/dcn20/dcn20_stream_encoder.c   |  12 +
 .../display/dc/dcn20/dcn20_stream_encoder.h   |   3 +
 .../dc/dcn30/dcn30_dio_stream_encoder.c       |   2 +
 .../dc/dcn30/dcn30_dio_stream_encoder.h       |  12 +
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    |   4 +
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    |   1 +
 .../drm/amd/display/dc/dml/display_mode_vba.c |   2 -
 .../gpu/drm/amd/display/dc/hdcp/hdcp_msg.c    |   1 +
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  11 +-
 .../amd/display/dc/inc/hw/stream_encoder.h    |   3 +
 .../gpu/drm/amd/display/dc/inc/link_dpcd.h    |  18 ++
 .../gpu/drm/amd/display/dc/inc/link_hwss.h    |  14 --
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   |  29 +++
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |   4 +-
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c |  65 +++++-  .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h |  14 +-
 .../gpu/drm/amd/display/dmub/src/dmub_dcn21.c |   5 +-
 .../gpu/drm/amd/display/dmub/src/dmub_dcn30.c |   5 +-
 .../drm/amd/display/dmub/src/dmub_dcn301.c    |   5 +-
 .../drm/amd/display/dmub/src/dmub_dcn302.c    |   5 +-
 .../drm/amd/display/dmub/src/dmub_dcn303.c    |   5 +-
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |  10 +
 .../amd/display/modules/power/power_helpers.c |  20 +-
 .../include/asic_reg/dcn/dcn_3_0_1_sh_mask.h  |   2 +
 .../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h  |   2 +
 include/drm/drm_dp_helper.h                   |  17 ++
 45 files changed, 1042 insertions(+), 403 deletions(-)  create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
 create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h

--
2.25.1

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