[PATCH V2 4/7] drm/amdgpu: fix the hang caused by PCIe link width switch

[Evan Quan]

SMU had set all the necessary fields for a link width switch
but the width switch wasn't occurring because the link was idle
in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width
switches to also be initiated while in L1 instead of waiting until
the link is back in L0.

Change-Id: I6315681f6fb194036b20991512dd88fa65bc0d56
Signed-off-by: Evan Quan <evan.quan at amd.com>
---
V1->V2:
  - limit the change for Navi10 only
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 2e1d12369cec..f31c331a1c48 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1432,6 +1432,15 @@ static void nv_apply_lc_spc_mode_wa(struct amdgpu_device *adev)
 	}
 }
 
+static void nv_apply_l1_link_width_reconfig_wa(struct amdgpu_device *adev)
+{
+	uint32_t reg_data = 0;
+
+	reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL);
+	reg_data |= PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK;
+	WREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL, reg_data);
+}
+
 static int nv_common_hw_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1440,6 +1449,9 @@ static int nv_common_hw_init(void *handle)
 	     (adev->asic_type <= CHIP_NAVI12))
 		nv_apply_lc_spc_mode_wa(adev);
 
+	if (adev->asic_type == CHIP_NAVI10)
+		nv_apply_l1_link_width_reconfig_wa(adev);
+
 	/* enable pcie gen2/3 link */
 	nv_pcie_gen3_enable(adev);
 	/* enable aspm */
-- 
2.29.0