[PATCH 1/1] drm/amdgpu: Read clock counter via MMIO to reduce delay (v4)

[Christian König]

Am 30.06.21 um 13:17 schrieb Liu, Monk:
> [AMD Official Use Only]
>
>>> And a preempt_enable(); here. This way the critical section is also not interrupted by a task switch.
> Do you mean put a "preempt_disable()" here ?

No? We need to disable preemption before the critical section and enable 
it again when we are done.

Or is the code called under a spinlock or similar? In that case this 
would be superfluous.

Anyway it is rather unlikely that the task is not scheduled again for 
the next 42 seconds.

Christian.

>
> Thanks
>
> ------------------------------------------
> Monk Liu | Cloud-GPU Core team
> ------------------------------------------
>
> -----Original Message-----
> From: Christian König <ckoenig.leichtzumerken at gmail.com>
> Sent: Wednesday, June 30, 2021 7:15 PM
> To: Wang, YuBiao <YuBiao.Wang at amd.com>; amd-gfx at lists.freedesktop.org
> Cc: Grodzovsky, Andrey <Andrey.Grodzovsky at amd.com>; Xiao, Jack <Jack.Xiao at amd.com>; Xu, Feifei <Feifei.Xu at amd.com>; Chen, Horace <Horace.Chen at amd.com>; Wang, Kevin(Yang) <Kevin1.Wang at amd.com>; Tuikov, Luben <Luben.Tuikov at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Quan, Evan <Evan.Quan at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>; Liu, Monk <Monk.Liu at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>
> Subject: Re: [PATCH 1/1] drm/amdgpu: Read clock counter via MMIO to reduce delay (v4)
>
> Am 30.06.21 um 12:10 schrieb YuBiao Wang:
>> [Why]
>> GPU timing counters are read via KIQ under sriov, which will introduce
>> a delay.
>>
>> [How]
>> It could be directly read by MMIO.
>>
>> v2: Add additional check to prevent carryover issue.
>> v3: Only check for carryover for once to prevent performance issue.
>> v4: Add comments of the rough frequency where carryover happens.
>>
>> Signed-off-by: YuBiao Wang <YuBiao.Wang at amd.com>
>> Acked-by: Horace Chen <horace.chen at amd.com>
>> ---
>>    drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 ++++++++++---
>>    1 file changed, 10 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index ff7e9f49040e..9355494002a1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -7609,7 +7609,7 @@ static int gfx_v10_0_soft_reset(void *handle)
>>    
>>    static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>>    {
>> -	uint64_t clock;
>> +	uint64_t clock, clock_lo, clock_hi, hi_check;
>>    
>>    	amdgpu_gfx_off_ctrl(adev, false);
>>    	mutex_lock(&adev->gfx.gpu_clock_mutex);
>> @@ -7620,8 +7620,15 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>>    			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
>>    		break;
>>    	default:
>> -		clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
>> -			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
> If you want to be extra sure you could add a preempt_disable(); here.
>
>> +		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
>> +		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
>> +		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
>> +		/* Carryover happens every 4 Giga time cycles counts which is roughly 42 secs */
>> +		if (hi_check != clock_hi) {
>> +			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
>> +			clock_hi = hi_check;
>> +		}
> And a preempt_enable(); here. This way the critical section is also not interrupted by a task switch.
>
> But either way the patch is Reviewed-by: Christian König <christian.koenig at amd.com>
>
> Regards,
> Christian.
>
>> +		clock = (uint64_t)clock_lo | ((uint64_t)clock_hi << 32ULL);
>>    		break;
>>    	}
>>    	mutex_unlock(&adev->gfx.gpu_clock_mutex);