Re: [PATCH 1/1] drm/amdgpu: Read clock counter via MMIO to reduce delay (v4)
jay at jcornwall.com
Wed Jun 30 14:15:37 UTC 2021
On Wed, Jun 30, 2021, at 05:10, YuBiao Wang wrote:
> GPU timing counters are read via KIQ under sriov, which will introduce
> a delay.
> It could be directly read by MMIO.
> v2: Add additional check to prevent carryover issue.
> v3: Only check for carryover for once to prevent performance issue.
> v4: Add comments of the rough frequency where carryover happens.
> Signed-off-by: YuBiao Wang <YuBiao.Wang at amd.com>
> Acked-by: Horace Chen <horace.chen at amd.com>
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index ff7e9f49040e..9355494002a1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7609,7 +7609,7 @@ static int gfx_v10_0_soft_reset(void *handle)
> static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> - uint64_t clock;
> + uint64_t clock, clock_lo, clock_hi, hi_check;
> amdgpu_gfx_off_ctrl(adev, false);
This clock can be read with gfxoff enabled.
Is the mutex relevant with this clock? It doesn't snapshot like RLC.
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