[PATCH 1/2] drm/amd/pm: Add LightSBR SMU MSG support
shaoyunl
shaoyun.liu at amd.com
Thu Mar 11 01:59:07 UTC 2021
This new MSG provide the interface for driver to enable/disable the Light Secondary Bus Reset
support from SMU. When enabled, SMU will only do minimum NBIO response to the SBR request and
leave the real HW reset to be handled by driver later. When disabled (default state),SMU will
pass the request to PSP for a HW reset
Signed-off-by: shaoyunl <shaoyun.liu at amd.com>
Change-Id: I5f0e48730d2b4b48fed8137aa57c683d5b3d1b9f
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 7 +++++++
drivers/gpu/drm/amd/pm/inc/arcturus_ppsmc.h | 7 +++++++
drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 +
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 ++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 13 +++++++++++++
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 ++
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 10 ++++++++++
7 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index c02ffbd1df76..5ac683fd0749 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1153,6 +1153,11 @@ struct pptable_funcs {
* parameters to defaults.
*/
int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
+
+ /**
+ * @set_light_sbr: Set light sbr mode for the SMU.
+ */
+ int (*set_light_sbr)(struct smu_context *smu, bool enable);
};
typedef enum {
@@ -1356,5 +1361,7 @@ ssize_t smu_sys_get_gpu_metrics(void *handle, void **table);
int smu_enable_mgpu_fan_boost(void *handle);
int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state);
+int smu_set_light_sbr(struct smu_context *smu, bool enable);
+
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/inc/arcturus_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/arcturus_ppsmc.h
index 79afb132164e..45f5d29bc705 100644
--- a/drivers/gpu/drm/amd/pm/inc/arcturus_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/inc/arcturus_ppsmc.h
@@ -120,6 +120,13 @@
#define PPSMC_MSG_ReadSerialNumTop32 0x40
#define PPSMC_MSG_ReadSerialNumBottom32 0x41
+/* paramater for MSG_LightSBR
+ * 1 -- Enable light secondary bus reset, only do nbio respond without further handling,
+ * leave driver to handle the real reset
+ * 0 -- Disable LightSBR, default behavior, SMU will pass the reset to PSP
+ */
+#define PPSMC_MSG_LightSBR 0x42
+
typedef uint32_t PPSMC_Result;
typedef uint32_t PPSMC_Msg;
#pragma pack(pop)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index e9a0bda98fd7..5bfb60f41dd4 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -224,6 +224,7 @@
__SMU_DUMMY_MAP(EnableDeterminism), \
__SMU_DUMMY_MAP(DisableDeterminism), \
__SMU_DUMMY_MAP(SetUclkDpmMode), \
+ __SMU_DUMMY_MAP(LightSBR), \
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index bf570a7af6a7..907e0967a9e8 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -295,5 +295,7 @@ int smu_v11_0_deep_sleep_control(struct smu_context *smu,
void smu_v11_0_interrupt_work(struct smu_context *smu);
+int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable);
+
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 6a6fafc11588..1202b9e7d0f9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2972,6 +2972,19 @@ int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state)
return ret;
}
+int smu_set_light_sbr(struct smu_context *smu, bool enable)
+{
+ int ret = 0;
+
+ mutex_lock(&smu->mutex);
+ if (smu->ppt_funcs->set_light_sbr)
+ ret = smu->ppt_funcs->set_light_sbr(smu, enable);
+ mutex_unlock(&smu->mutex);
+
+ return ret;
+}
+
+
static const struct amd_pm_funcs swsmu_pm_funcs = {
/* export for sysfs */
.set_fan_control_mode = smu_pp_set_fan_control_mode,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index f76d1b8aeecc..f82dd8a5c773 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -142,6 +142,7 @@ static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1),
MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1),
+ MSG_MAP(LightSBR, PPSMC_MSG_LightSBR, 0),
};
static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
@@ -2363,6 +2364,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.deep_sleep_control = smu_v11_0_deep_sleep_control,
.get_fan_parameters = arcturus_get_fan_parameters,
.interrupt_work = smu_v11_0_interrupt_work,
+ .set_light_sbr = smu_v11_0_set_light_sbr,
};
void arcturus_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 97acb04e1b5a..635bd5da2133 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1603,6 +1603,16 @@ int smu_v11_0_mode1_reset(struct smu_context *smu)
return ret;
}
+int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable)
+{
+ int ret = 0;
+
+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL);
+
+ return ret;
+}
+
+
int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *min, uint32_t *max)
{
--
2.17.1
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