[PATCH 2/2] drm/amdgpu: Introduce new SETUP_TMR interface

[Zeng, Oak]

[AMD Official Use Only - Internal Distribution Only]

Hello all,

Can someone help to review below patches? We verified with firmware team and want to check-in together with psp firmware

Regards,
Oak



On 2021-03-12, 4:24 PM, "Zeng, Oak" <Oak.Zeng at amd.com> wrote:

    This new interface passes both virtual and physical address
    to PSP. It is backword compatible with old interface.

    Signed-off-by: Oak Zeng <Oak.Zeng at amd.com>
    ---
     drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 ++++++++++---
     drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 11 ++++++++++-
     2 files changed, 20 insertions(+), 4 deletions(-)

    diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
    index cd3eda9..99e1a3e 100644
    --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
    +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
    @@ -328,8 +328,13 @@ psp_cmd_submit_buf(struct psp_context *psp,

     static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
      struct psp_gfx_cmd_resp *cmd,
    - uint64_t tmr_mc, uint32_t size)
    + uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
     {
    +struct amdgpu_device *adev = psp->adev;
    +uint32_t size = amdgpu_bo_size(tmr_bo);
    +uint64_t tmr_pa = amdgpu_bo_gpu_offset(tmr_bo) +
    +adev->vm_manager.vram_base_offset - adev->gmc.vram_start;
    +
     if (amdgpu_sriov_vf(psp->adev))
     cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
     else
    @@ -337,6 +342,9 @@ static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
     cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
     cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
     cmd->cmd.cmd_setup_tmr.buf_size = size;
    +cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
    +cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
    +cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
     }

     static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
    @@ -456,8 +464,7 @@ static int psp_tmr_load(struct psp_context *psp)
     if (!cmd)
     return -ENOMEM;

    -psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
    -     amdgpu_bo_size(psp->tmr_bo));
    +psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
     DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
      amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);

    diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
    index a41b054..604a1c1 100644
    --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
    +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
    @@ -170,10 +170,19 @@ struct psp_gfx_cmd_setup_tmr
         uint32_t        buf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
         uint32_t        buf_phy_addr_hi;       /* bits [63:32] of GPU Virtual address of TMR buffer */
         uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB) */
    +    union {
    +struct {
    +uint32_tsriov_enabled:1; /* whether the device runs under SR-IOV*/
    +uint32_tvirt_phy_addr:1; /* driver passes both virtual and physical address to PSP*/
    +uint32_treserved:30;
    +} bitfield;
    +uint32_t        tmr_flags;
    +    };
    +    uint32_t        system_phy_addr_lo;        /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */
    +    uint32_t        system_phy_addr_hi;        /* bits [63:32] of system physical address of TMR buffer */

     };

    -
     /* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
     enum psp_gfx_fw_type {
     GFX_FW_TYPE_NONE        = 0,    /* */
    --
    2.7.4