[PATCH] drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headers

[Alex Deucher]

On Fri, Mar 26, 2021 at 9:49 AM Tom St Denis <tom.stdenis at amd.com> wrote:
>
> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  .../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h   | 6 ++++++
>  .../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h  | 9 +++++++++
>  2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
> index 0102487a2c5f..f21554a1c86c 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
> @@ -6955,6 +6955,12 @@
>  #define mmCP_CE_IB2_BASE_HI_BASE_IDX                                                                   1
>  #define mmCP_CE_IB2_BUFSZ                                                                              0x20cb
>  #define mmCP_CE_IB2_BUFSZ_BASE_IDX                                                                     1
> +#define mmCP_IB1_BASE_LO                                                                               0x20cc
> +#define mmCP_IB1_BASE_LO_BASE_IDX                                                                      1
> +#define mmCP_IB1_BASE_HI                                                                               0x20cd
> +#define mmCP_IB1_BASE_HI_BASE_IDX                                                                      1
> +#define mmCP_IB1_BUFSZ                                                                                 0x20ce
> +#define mmCP_IB1_BUFSZ_BASE_IDX                                                                        1
>  #define mmCP_IB2_BASE_LO                                                                               0x20cf
>  #define mmCP_IB2_BASE_LO_BASE_IDX                                                                      1
>  #define mmCP_IB2_BASE_HI                                                                               0x20d0
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
> index 4d2a1432c121..a827b0ff8905 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
> @@ -25818,6 +25818,15 @@
>  //CP_CE_IB2_BUFSZ
>  #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT                                                                     0x0
>  #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK                                                                       0x000FFFFFL
> +//CP_IB1_BASE_LO
> +#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT                                                                    0x2
> +#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK                                                                      0xFFFFFFFCL
> +//CP_IB1_BASE_HI
> +#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT                                                                    0x0
> +#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK                                                                      0x0000FFFFL
> +//CP_IB1_BUFSZ
> +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                                                                        0x0
> +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                                                                          0x000FFFFFL
>  //CP_IB2_BASE_LO
>  #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT                                                                    0x2
>  #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK                                                                      0xFFFFFFFCL
> --
> 2.30.2
>
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