[PATCH] drm/amd/display: add DMCUB trace irq support for DCN302
Ma, Hanghong
Hanghong.Ma at amd.com
Mon Mar 29 15:37:44 UTC 2021
[AMD Public Use]
Looks good to me.
Reviewed-by: Leo (Hanghong) Ma <hanghong.ma at amd.com>
Thanks,
Leo
-----Original Message-----
From: Chen, Guchun <Guchun.Chen at amd.com>
Sent: Friday, March 26, 2021 10:08 AM
To: amd-gfx at lists.freedesktop.org; Ma, Hanghong <Hanghong.Ma at amd.com>; Wentland, Harry <Harry.Wentland at amd.com>; Lin, Wayne <Wayne.Lin at amd.com>; Yin, Tianci (Rico) <Tianci.Yin at amd.com>
Cc: Chen, Guchun <Guchun.Chen at amd.com>
Subject: [PATCH] drm/amd/display: add DMCUB trace irq support for DCN302
Otherwise, below errors will be found on DIMGREY_CAVEFISH with DCN302.
Error log observed in driver load:
[drm:amdgpu_dm_irq_register_interrupt [amdgpu]] *ERROR* DM_IRQ: invalid irq_source: 0!
Error observed in mode1_rest sequence:
[ 27.265920] #PF: supervisor read access in kernel mode
[ 27.265941] #PF: error_code(0x0000) - not-present page
[ 27.265956] PGD 0 P4D 0
[ 27.265967] Oops: 0000 [#1] SMP NOPTI
[ 27.265979] CPU: 0 PID: 1360 Comm: cat Tainted: G W 5.11.0-99b3786c1770 #20210323
[ 27.266005] Hardware name: System manufacturer System Product Name/PRIME Z390-A, BIOS 1401 11/26/2019
[ 27.266033] RIP: 0010:dal_irq_service_ack+0x25/0x60 [amdgpu]
[ 27.266203] Code: 5d 5d c3 66 90 0f 1f 44 00 00 55 83 fe 61 48 89 e5 77 27 89 f0 48 8d 04 40 48 c1 e0 04 48 03 47 08 74 17 48 8b 50 28 48 89 c6 <48> 8b 52 08 48 85 d2 74 20 e8 1d 64 45 c9 5d c3 89 f2 48 c7 c7 f0
[ 27.266248] RSP: 0018:ffffa115824a3c08 EFLAGS: 00010082
[ 27.266270] RAX: ffffffffc0942c10 RBX: ffffffffc0942c10 RCX: 0000000000000000
[ 27.266288] RDX: 0000000000000000 RSI: ffffffffc0942c10 RDI: ffff88d509cba7a0
[ 27.266312] RBP: ffffa115824a3c08 R08: 0000000000000000 R09: 0000000000000001
[ 27.266335] R10: ffffa115824a3b20 R11: ffffa115824a3b58 R12: ffff88d509cba7a0
[ 27.266353] R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000246
[ 27.266377] FS: 00007fb3e2438580(0000) GS:ffff88d50dc00000(0000) knlGS:0000000000000000
[ 27.266402] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 27.266417] CR2: 0000000000000008 CR3: 000000083e5ac006 CR4: 00000000003706f0
[ 27.266441] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 27.266464] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[ 27.266483] Call Trace:
[ 27.266491] dal_irq_service_set+0x31/0x80 [amdgpu]
[ 27.266639] dc_interrupt_set+0x24/0x30 [amdgpu]
[ 27.266775] amdgpu_dm_set_dmub_trace_irq_state+0x22/0x30 [amdgpu]
[ 27.266920] amdgpu_irq_update+0x57/0xa0 [amdgpu]
[ 27.267030] amdgpu_irq_gpu_reset_resume_helper+0x64/0xa0 [amdgpu]
[ 27.267135] amdgpu_do_asic_reset+0x211/0x420 [amdgpu]
[ 27.267232] amdgpu_device_gpu_recover+0x517/0xa70 [amdgpu]
[ 27.267325] gpu_recover_get+0x2e/0x60 [amdgpu]
[ 27.267421] simple_attr_read+0x6b/0x130
[ 27.267441] debugfs_attr_read+0x49/0x70
[ 27.267454] full_proxy_read+0x5c/0x90
[ 27.267474] vfs_read+0xa1/0x190
[ 27.267486] ksys_read+0xa7/0xe0
[ 27.267501] __x64_sys_read+0x1a/0x20
[ 27.267521] do_syscall_64+0x37/0x80
[ 27.267541] entry_SYSCALL_64_after_hwframe+0x44/0xa9
[ 27.267562] RIP: 0033:0x7fb3e2356142
Signed-off-by: Guchun Chen <guchun.chen at amd.com>
---
.../dc/irq/dcn302/irq_service_dcn302.c | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
index 2313a5664f44..40fd34fb1d5e 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
@@ -50,6 +50,8 @@ static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_servi
return DC_IRQ_SOURCE_VBLANK5;
case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK6;
+ case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT:
+ return DC_IRQ_SOURCE_DMCUB_OUTBOX0;
case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
return DC_IRQ_SOURCE_DC1_VLINE0;
case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
@@ -166,6 +168,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
.ack = NULL
};
+static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
static const struct irq_source_info_funcs vline0_irq_info_funcs = {
.set = NULL,
.ack = NULL
@@ -181,6 +188,9 @@ static const struct irq_source_info_funcs vline0_irq_info_funcs = {
BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## reg_name
+#define SRI_DMUB(reg_name)\
+ BASE(mm ## reg_name ## _BASE_IDX) + \
+ mm ## reg_name
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
.enable_reg = SRI(reg1, block, reg_num),\ @@ -193,7 +203,26 @@ static const struct irq_source_info_funcs vline0_irq_info_funcs = {
.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
+#define dmub_trace_int_entry()\
+ [DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\
+ IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\
+ DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\
+ .funcs = &dmub_trace_irq_info_funcs\
+ }
+#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
+ .enable_reg = SRI_DMUB(reg1),\
+ .enable_mask = \
+ reg1 ## __ ## mask1 ## _MASK,\
+ .enable_value = {\
+ reg1 ## __ ## mask1 ## _MASK,\
+ ~reg1 ## __ ## mask1 ## _MASK \
+ },\
+ .ack_reg = SRI_DMUB(reg2),\
+ .ack_mask = \
+ reg2 ## __ ## mask2 ## _MASK,\
+ .ack_value = \
+ reg2 ## __ ## mask2 ## _MASK \
#define hpd_int_entry(reg_num)\
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
@@ -348,6 +377,7 @@ static const struct irq_source_info irq_source_info_dcn302[DAL_IRQ_SOURCES_NUMBE
vline0_int_entry(2),
vline0_int_entry(3),
vline0_int_entry(4),
+ dmub_trace_int_entry(),
};
static const struct irq_service_funcs irq_service_funcs_dcn302 = {
--
2.17.1
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