[PATCH] drm/amdgpu: Init GFX10_ADDR_CONFIG for VCN v3 in DPG mode.

[Leo Liu]

On 2021-05-05 2:17 p.m., Alex Deucher wrote:
> Applied.  Thanks!  Do we need a similar fix for other VCN variants?

VCN3 is the only one missing that.

Regards,

Leo


>
> Alex
>
> On Tue, May 4, 2021 at 10:14 PM Leo Liu <leo.liu at amd.com> wrote:
>> Reviewed-and-Tested by: Leo Liu <leo.liu at amd.com>
>>
>> On 2021-05-04 9:27 p.m., Bas Nieuwenhuizen wrote:
>>> Otherwise tiling modes that require the values form this field
>>> (In particular _*_X) would be corrupted upon video decode.
>>>
>>> Copied from the VCN v2 code.
>>>
>>> Fixes: 99541f392b4d ("drm/amdgpu: add mc resume DPG mode for VCN3.0")
>>> Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
>>> ---
>>>    drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++++
>>>    1 file changed, 4 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>>> index 3f15bf34123a..cf165ab5dd26 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>>> @@ -589,6 +589,10 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
>>>        WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
>>>                        VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),
>>>                        AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
>>> +
>>> +     /* VCN global tiling registers */
>>> +     WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
>>> +             UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
>>>    }
>>>
>>>    static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)