[PATCH 00/20] DC Patches May 17, 2021

Fri May 14 19:32:42 UTC 2021

[AMD Public Use]

Hi all,

This week this patchset was tested on the following systems:

HP Envy 360, with Ryzen 5 4500U, on the following display types: eDP 1080p 60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)

Sapphire Pulse RX5700XT on the following display types:
4k 60hz  (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)

Reference AMD RX6800 on the following display types:
4k 60hz  (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)

Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz on all systems.

Tested-by: Daniel Wheeler <daniel.wheeler at amd.com>

Thank you,

Dan Wheeler
Technologist  |  AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
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-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Stylon Wang
Sent: May 14, 2021 12:50 AM
To: amd-gfx at lists.freedesktop.org
Cc: Wang, Chao-kai (Stylon) <Stylon.Wang at amd.com>; Brol, Eryk <Eryk.Brol at amd.com>; Li, Sun peng (Leo) <Sunpeng.Li at amd.com>; Wentland, Harry <Harry.Wentland at amd.com>; Zhuo, Qingqing <Qingqing.Zhuo at amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira at amd.com>; Jacob, Anson <Anson.Jacob at amd.com>; Pillai, Aurabindo <Aurabindo.Pillai at amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha at amd.com>; R, Bindu <Bindu.R at amd.com>
Subject: [PATCH 00/20] DC Patches May 17, 2021

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* DC v3.2.136
* Improvements across DP, DMUB, code documentation, suspend/resume, etc

--

Anthony Koo (1):
  drm/amd/display: [FW Promotion] Release 0.0.66

Aric Cyr (1):
  drm/amd/display: 3.2.136

Bhawanpreet Lakha (1):
  drm/amd/display: Add Overflow check to skip MALL

Chris Park (1):
  drm/amd/display: Disconnect non-DP with no EDID

George Shen (1):
  drm/amd/display: Minor refactor of DP PHY test automation

Hugo Hu (1):
  drm/amd/display: treat memory as a single-channel for asymmetric
    memory V3

Nikola Cornij (1):
  drm/amd/display: Use the correct max downscaling value for DCN3.x
    family

Rodrigo Siqueira (4):
  drm/amd/display: Add documentation for power gate plane
  drm/amd/display: Remove legacy comments
  drm/amd/display: Add kernel-doc to some hubp functions
  drm/amd/display: Document set RECOUT operation

Wayne Lin (2):
  drm/amd/display: Refactor suspend/resume of Secure display
  drm/amd/display: Avoid get/put vblank when stream disabled

Wenjing Liu (4):
  drm/amd/display: determine dp link encoding format from link settings
  drm/amd/display: decide link training settings based on channel coding
  drm/amd/display: rename perform_link_training_int function
  drm/amd/display: consider channel coding in configure lttpr mode

Wyatt Wood (2):
  drm/amd/display: Add get_current_time interface to dmub_srv
  drm/amd/display: Refactor and add visual confirm for HW Flip Queue

Zhan Liu (1):
  drm/amd/display: Correct DPCD revision for eDP v1.4

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  32 +--  .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c |  63 +----
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h |   4 -
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |  48 +++-
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  39 +--
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  18 ++  .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 106 +++++---
 drivers/gpu/drm/amd/display/dc/dc.h           |   4 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |   5 +
 .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c |  49 ++--  .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |  13 +  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 229 +++++-------------
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |   6 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |   1 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |   5 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  28 ++-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h    |   5 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   1 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c |   8 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   1 +
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    |   9 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |   1 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c  |   2 +-
 .../drm/amd/display/dc/dcn30/dcn30_resource.c |   7 +-
 .../drm/amd/display/dc/dcn301/dcn301_init.c   |   1 +
 .../amd/display/dc/dcn301/dcn301_resource.c   |   7 +-
 .../amd/display/dc/dcn302/dcn302_resource.c   |   7 +-
 drivers/gpu/drm/amd/display/dc/dm_services.h  |   1 -
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h   |   6 +
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   |   3 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   4 +
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   |   1 +
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |   4 +-
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c |   5 +
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h |   5 +-
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |   1 +
 .../amd/display/include/link_service_types.h  |   1 +
 39 files changed, 380 insertions(+), 353 deletions(-)

--
2.25.1

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