[PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang

[Huang Rui]

On Fri, May 14, 2021 at 10:13:55PM +0800, Alex Deucher wrote:
> On Fri, May 14, 2021 at 4:20 AM <changfeng.zhu at amd.com> wrote:
> >
> > From: changzhu <Changfeng.Zhu at amd.com>
> >
> > From: Changfeng <Changfeng.Zhu at amd.com>
> >
> > There is problem with 3DCGCG firmware and it will cause compute test
> > hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid
> > compute hang.
> >
> > Change-Id: Ic7d3c7922b2b32f7ac5193d6a4869cbc5b3baa87
> > Signed-off-by: Changfeng <Changfeng.Zhu at amd.com>
> 
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> 
> WIth this applied, can we re-enable the additional compute queues?
> 

I think so.

Changfeng, could you please confirm this on all raven series?

Patch is Reviewed-by: Huang Rui <ray.huang at amd.com>

> Alex
> 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++++---
> >  drivers/gpu/drm/amd/amdgpu/soc15.c    |  2 --
> >  2 files changed, 7 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 22608c45f07c..feaa5e4a5538 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -4947,7 +4947,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
> >         amdgpu_gfx_rlc_enter_safe_mode(adev);
> >
> >         /* Enable 3D CGCG/CGLS */
> > -       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
> > +       if (enable) {
> >                 /* write cmd to clear cgcg/cgls ov */
> >                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
> >                 /* unset CGCG override */
> > @@ -4959,8 +4959,12 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
> >                 /* enable 3Dcgcg FSM(0x0000363f) */
> >                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
> >
> > -               data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> > -                       RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
> > +               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
> > +                       data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> > +                               RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
> > +               else
> > +                       data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT;
> > +
> >                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
> >                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
> >                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > index 4b660b2d1c22..080e715799d4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > @@ -1393,7 +1393,6 @@ static int soc15_common_early_init(void *handle)
> >                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> >                                 AMD_CG_SUPPORT_GFX_MGLS |
> >                                 AMD_CG_SUPPORT_GFX_CP_LS |
> > -                               AMD_CG_SUPPORT_GFX_3D_CGCG |
> >                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
> >                                 AMD_CG_SUPPORT_GFX_CGCG |
> >                                 AMD_CG_SUPPORT_GFX_CGLS |
> > @@ -1413,7 +1412,6 @@ static int soc15_common_early_init(void *handle)
> >                                 AMD_CG_SUPPORT_GFX_MGLS |
> >                                 AMD_CG_SUPPORT_GFX_RLC_LS |
> >                                 AMD_CG_SUPPORT_GFX_CP_LS |
> > -                               AMD_CG_SUPPORT_GFX_3D_CGCG |
> >                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
> >                                 AMD_CG_SUPPORT_GFX_CGCG |
> >                                 AMD_CG_SUPPORT_GFX_CGLS |
> > --
> > 2.17.1
> >
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