[PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers

[Zhou, Peng Ju]

[AMD Official Use Only - Internal Distribution Only]

Hi @Zhao, Victor/@Deng, Emily

Can you help to answer Alex's question,?
Because this patch originally from @Zhao, Victor, it's hard for me to explain the question.

Alex's question:
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> >         case CHIP_NAVI12:
> >                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> >                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> > -               amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> >                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
> > +               amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> 
> Is it safe to change the order like this on bare metal?  Please look at what was
> done for vega and sienna cichlid.  Something like that is probably a better bet.


---------------------------------------------------------------------- 
BW
Pengju Zhou




> -----Original Message-----
> From: Alex Deucher <alexdeucher at gmail.com>
> Sent: Thursday, May 20, 2021 11:47 AM
> To: Zhou, Peng Ju <PengJu.Zhou at amd.com>
> Cc: amd-gfx list <amd-gfx at lists.freedesktop.org>; Zhao, Victor
> <Victor.Zhao at amd.com>
> Subject: Re: [PATCH v5 09/10] drm/amdgpu: Use PSP to program
> IH_RB_CNTL* registers
> 
> On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou <PengJu.Zhou at amd.com>
> wrote:
> >
> > use psp to program IH_RB_CNTL* if indirect access for ih enabled in
> > SRIOV environment.
> >
> > Signed-off-by: Victor <Victor.Zhao at amd.com>
> > Signed-off-by: Peng Ju Zhou <PengJu.Zhou at amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +++++++++++++++++--
> >  drivers/gpu/drm/amd/amdgpu/nv.c        |  2 +-
> >  2 files changed, 18 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > index f4e4040bbd25..2e69cf8db072 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > @@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct
> amdgpu_device *adev,
> >         /* enable_intr field is only valid in ring0 */
> >         if (ih == &adev->irq.ih)
> >                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ?
> 1 : 0));
> > -       WREG32(ih_regs->ih_rb_cntl, tmp);
> > +       if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> > +               if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> > +                       DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> > +                       return -ETIMEDOUT;
> > +               }
> > +       } else {
> > +               WREG32(ih_regs->ih_rb_cntl, tmp);
> > +       }
> >
> >         if (enable) {
> >                 ih->enabled = true;
> > @@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct
> amdgpu_device *adev,
> >                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL,
> WPTR_OVERFLOW_ENABLE, 0);
> >                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE,
> 1);
> >         }
> > -       WREG32(ih_regs->ih_rb_cntl, tmp);
> > +
> > +       if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> > +               if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> > +                       DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> > +                       return -ETIMEDOUT;
> > +               }
> > +       } else {
> > +               WREG32(ih_regs->ih_rb_cntl, tmp);
> > +       }
> >
> >         if (ih == &adev->irq.ih) {
> >                 /* set the ih ring 0 writeback address whether it's
> > enabled or not */ diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
> > b/drivers/gpu/drm/amd/amdgpu/nv.c index a9ad28fb55b3..b9c9c4d4606c
> > 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> >         case CHIP_NAVI12:
> >                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> >                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> > -               amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> >                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
> > +               amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> 
> Is it safe to change the order like this on bare metal?  Please look at what was
> done for vega and sienna cichlid.  Something like that is probably a better bet.
> 
> Alex
> 
> 
> >                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
> >                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> >                 if (adev->enable_virtual_display ||
> > amdgpu_sriov_vf(adev))
> > --
> > 2.17.1
> >
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