[PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack

[Deng, Emily]

[AMD Official Use Only]

Reviewed-by: Emily Deng <Emily.Deng at amd.com>

>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Jingwen
>Chen
>Sent: Wednesday, May 26, 2021 2:55 PM
>To: amd-gfx at lists.freedesktop.org
>Cc: Chen, JingWen <JingWen.Chen2 at amd.com>; Zhao, Victor
><Victor.Zhao at amd.com>; Liu, Monk <Monk.Liu at amd.com>
>Subject: [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack
>
>From: Victor Zhao <Victor.Zhao at amd.com>
>
>save psp ring wptr in SRIOV to avoid attack to avoid extra changes to
>MP0_SMN_C2PMSG_102 reg
>
>Change-Id: Idee78e8c1c781463048f2f6311fdc70488ef05b2
>Signed-off-by: Victor Zhao <Victor.Zhao at amd.com>
>Signed-off-by: Jingwen Chen <Jingwen.Chen2 at amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
>drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 3 ++-
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 3 ++-
> 4 files changed, 6 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>index 55378c6b9722..20e06b3ec686 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>@@ -2701,6 +2701,7 @@ int psp_ring_cmd_submit(struct psp_context *psp,
>       /* Update the write Pointer in DWORDs */
>       psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) %
>ring_size_dw;
>       psp_ring_set_wptr(psp, psp_write_ptr_reg);
>+      ring->ring_wptr = psp_write_ptr_reg;
>       return 0;
> }
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>index 46a5328e00e0..60aa99a39a74 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>@@ -76,6 +76,7 @@ struct psp_ring
>       uint64_t                        ring_mem_mc_addr;
>       void                            *ring_mem_handle;
>       uint32_t                        ring_size;
>+      uint32_t                        ring_wptr;
> };
>
> /* More registers may will be supported */ diff --git
>a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>index 1f2e7e35c91e..4a32b0c84ef4 100644
>--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>@@ -474,6 +474,7 @@ static int psp_v11_0_ring_create(struct psp_context
>*psp,
>                       return ret;
>               }
>
>+              ring->ring_wptr = 0;
>               /* Write low address of the ring to C2PMSG_102 */
>               psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
>               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102,
>psp_ring_reg); @@ -733,7 +734,7 @@ static uint32_t
>psp_v11_0_ring_get_wptr(struct psp_context *psp)
>       struct amdgpu_device *adev = psp->adev;
>
>       if (amdgpu_sriov_vf(adev))
>-              data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
>+              data = psp->km_ring.ring_wptr;
>       else
>               data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>index f2e725f72d2f..160f78eb6403 100644
>--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>@@ -237,6 +237,7 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
>                       return ret;
>               }
>
>+              ring->ring_wptr = 0;
>               /* Write low address of the ring to C2PMSG_102 */
>               psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
>               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102,
>psp_ring_reg); @@ -379,7 +380,7 @@ static uint32_t
>psp_v3_1_ring_get_wptr(struct psp_context *psp)
>       struct amdgpu_device *adev = psp->adev;
>
>       if (amdgpu_sriov_vf(adev))
>-              data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
>+              data = psp->km_ring.ring_wptr;
>       else
>               data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
>       return data;
>--
>2.25.1
>
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