[PATCH] drm/amdgpu: Fix Gstreamer api vaapih264enc missing
Li, Xin (Justin)
Xin2.Li at amd.com
Thu May 27 07:17:50 UTC 2021
Hi, friends.
My apologize for this patch.
I’ve ported this patch from another branch to fix gstreamer’s lack of “vaapi264enc”, currently this ported patch did fix that issue. However, since this patch is ported from another branch, I might need to do some alternations and audits mainly in its commit messages. I will file another review right after my fixes.
Thank you all for you time.
BR,
Justin
From: Liu, Monk <Monk.Liu at amd.com>
Date: Thursday, May 27, 2021 at 07:57
To: Li, Xin (Justin) <Xin2.Li at amd.com>, amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Li, Xin (Justin) <Xin2.Li at amd.com>, Deucher, Alexander <Alexander.Deucher at amd.com>, Min, Frank <Frank.Min at amd.com>, Koenig, Christian <Christian.Koenig at amd.com>
Subject: RE: [PATCH] drm/amdgpu: Fix Gstreamer api vaapih264enc missing
[AMD Official Use Only]
Looks it lack enough background for people to review:
- if (adev->vcn.inst[i].ring_dec.sched.ready)
+ if (adev->vcn.inst[i].ring_dec.sched.ready ||
+ (adev->asic_type == CHIP_NAVI12 &&
+ amdgpu_sriov_vf(adev)))
++num_rings;
[ml] why for SRIOV navi12 is forced to have those DEC rings ? since SRIOV navi12 have no decode capability , any explain here ?
- if (amdgpu_is_tmz(adev))
- dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
[ML] why this is removed ? is it related to your issue ?
Thanks
------------------------------------------
Monk Liu | Cloud-GPU Core team
------------------------------------------
-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Li, Xin (Justin)
Sent: Wednesday, May 26, 2021 6:13 PM
To: amd-gfx at lists.freedesktop.org
Cc: Li, Xin (Justin) <Xin2.Li at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Min, Frank <Frank.Min at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>
Subject: [PATCH] drm/amdgpu: Fix Gstreamer api vaapih264enc missing
since vcn decoding ring is not required, so just disable it.
Cc: Alex.Deucher <alexander.deucher at amd.com>
Cc: Christian.Konig <christian.koenig at amd.com>
Signed-off-by: Li.Xin.Justin <xin2.li at amd.com>
Signed-off-by: Frank.Min <Frank.Min at amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 25 ++++++++++++++-----------
2 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 524e4fe5efe8..614e6b06e94e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -427,7 +427,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
if (adev->uvd.harvest_config & (1 << i))
continue;
- if (adev->vcn.inst[i].ring_dec.sched.ready)
+ if (adev->vcn.inst[i].ring_dec.sched.ready ||
+ (adev->asic_type == CHIP_NAVI12 &&
+ amdgpu_sriov_vf(adev)))
++num_rings;
}
ib_start_alignment = 16;
@@ -770,8 +772,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
- if (amdgpu_is_tmz(adev))
- dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
vm_size -= AMDGPU_VA_RESERVED_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 8af567c546db..dc8a36766c4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -220,17 +220,20 @@ static int vcn_v2_0_hw_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
- int i, r;
+ int i, r = -1;
adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
ring->doorbell_index, 0);
- if (amdgpu_sriov_vf(adev))
+ if (amdgpu_sriov_vf(adev)) {
vcn_v2_0_start_sriov(adev);
-
- r = amdgpu_ring_test_helper(ring);
- if (r)
- goto done;
+ if (adev->asic_type == CHIP_NAVI12)
+ ring->sched.ready = false;
+ } else {
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ goto done;
+ }
//Disable vcn decode for sriov
if (amdgpu_sriov_vf(adev))
@@ -245,8 +248,11 @@ static int vcn_v2_0_hw_init(void *handle)
done:
if (!r)
- DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
- (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
+ DRM_INFO("VCN %s encode initialized successfully(under %s).\n",
+ (adev->asic_type == CHIP_NAVI12 &&
+ amdgpu_sriov_vf(adev))?"":"decode and",
+ (adev->pg_flags &
+ AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
return r;
}
@@ -1721,9 +1727,6 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
- if (amdgpu_sriov_vf(adev))
- return 0;
-
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 4);
if (r)
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx at lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cmonk.liu%40amd.com%7Cb86e27d9b55f429b352308d9202ee408%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637576208056272141%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=cMllN28FN56voTpWwdnMmBB3CGXezs%2FaEwflSZD6qr4%3D&reserved=0
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20210527/4216cec7/attachment-0001.htm>
More information about the amd-gfx
mailing list