[PATCH] drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9

[Christian König]

Am 04.11.21 um 03:55 schrieb YuBiao Wang:
> [Why]
> For Vega10, disabling gart of gfxhub and mmhub could mess up KIQ and PSP
> under sriov mode, and lead to DMAR on host side.
>
> [How]
> Skip writing GMC registers under sriov.
>
> Signed-off-by: YuBiao Wang <YuBiao.Wang at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 26 +++++++++++++-----------
>   1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index bda1542ef1dd..f9a7349eb601 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -348,18 +348,20 @@ static void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
>   		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
>   				    i * hub->ctx_distance, 0);
>   
> -	/* Setup TLB control */
> -	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
> -	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
> -	tmp = REG_SET_FIELD(tmp,
> -				MC_VM_MX_L1_TLB_CNTL,
> -				ENABLE_ADVANCED_DRIVER_MODEL,
> -				0);
> -	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
> -
> -	/* Setup L2 cache */
> -	WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
> -	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
> +	if (!amdgpu_sriov_vf(adev)) {

Maybe make that an "if (amdgpu_sriov_vf(adev)) return", but in general 
feel free to add an Acked-by: Christian König <christian.koenig at amd.com> 
to the patch.

Additional to that the patch should probably be send to the public 
mailing list instead.

Regards,
Christian.

> +		/* Setup TLB control */
> +		tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
> +		tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
> +		tmp = REG_SET_FIELD(tmp,
> +					MC_VM_MX_L1_TLB_CNTL,
> +					ENABLE_ADVANCED_DRIVER_MODEL,
> +					0);
> +		WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
> +
> +		/* Setup L2 cache */
> +		WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
> +		WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
> +	}
>   }
>   
>   /**