[PATCH] drm/amd/pm: Correct DPMS disable IP version check

[Alex Deucher]

On Thu, Nov 4, 2021 at 12:09 PM Mario Limonciello
<mario.limonciello at amd.com> wrote:
>
> Previously there was a check based on chip # for chips that aligned to
> >=CHIP_NAVI10 to have RLC stopped as part of DPMS check.  This was because
> of gfxclk being controlled by RLC in the newer designs.
>
> As part of IP version checking though, this got changed to match IP
> version for SMU.  Because Renoir designs also include smu11 that meant
> that even GFX9 started to stop RLC earlier.
>
> Adjust to match GFX IP version instead of SMU IP version to restore the
> previous behavior.
>
> Fixes: a8967967f6a5 ("drm/amdgpu/amdgpu_smu: convert to IP version checking").
> Signed-off-by: Mario Limonciello <mario.limonciello at amd.com>

Good catch.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 821ae6e78703..01168b8955bf 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1468,7 +1468,7 @@ static int smu_disable_dpms(struct smu_context *smu)
>                         dev_err(adev->dev, "Failed to disable smu features.\n");
>         }
>
> -       if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0) &&
> +       if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0) &&
>             adev->gfx.rlc.funcs->stop)
>                 adev->gfx.rlc.funcs->stop(adev);
>
> --
> 2.25.1
>