[PATCH 1/2] drm/amdkfd: convert to IP-based version checking
Felix Kuehling
felix.kuehling at amd.com
Mon Nov 8 22:29:13 UTC 2021
Am 2021-11-05 um 3:58 p.m. schrieb Graham Sider:
> Patches to change KFD to use IP versions rather than asic_type.
> Converting IP version checking in main switch statements.
>
> Signed-off-by: Graham Sider <Graham.Sider at amd.com>
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 124 +++++++++---------
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 56 ++++----
> drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 52 ++++----
> .../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 56 ++++----
> drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 54 ++++----
> 5 files changed, 189 insertions(+), 153 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> index 1dc6cb7446e0..500bc7e40309 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> @@ -1377,67 +1377,71 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
> pcache_info = vegam_cache_info;
> num_of_cache_types = ARRAY_SIZE(vegam_cache_info);
> break;
> - case CHIP_VEGA10:
> - pcache_info = vega10_cache_info;
> - num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
> - break;
> - case CHIP_VEGA12:
> - pcache_info = vega12_cache_info;
> - num_of_cache_types = ARRAY_SIZE(vega12_cache_info);
> - break;
> - case CHIP_VEGA20:
> - case CHIP_ARCTURUS:
> - pcache_info = vega20_cache_info;
> - num_of_cache_types = ARRAY_SIZE(vega20_cache_info);
> - break;
> - case CHIP_ALDEBARAN:
> - pcache_info = aldebaran_cache_info;
> - num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info);
> - break;
> - case CHIP_RAVEN:
> - pcache_info = raven_cache_info;
> - num_of_cache_types = ARRAY_SIZE(raven_cache_info);
> - break;
> - case CHIP_RENOIR:
> - pcache_info = renoir_cache_info;
> - num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
> - break;
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_CYAN_SKILLFISH:
> - pcache_info = navi10_cache_info;
> - num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
> - break;
> - case CHIP_NAVI14:
> - pcache_info = navi14_cache_info;
> - num_of_cache_types = ARRAY_SIZE(navi14_cache_info);
> - break;
> - case CHIP_SIENNA_CICHLID:
> - pcache_info = sienna_cichlid_cache_info;
> - num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info);
> - break;
> - case CHIP_NAVY_FLOUNDER:
> - pcache_info = navy_flounder_cache_info;
> - num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info);
> - break;
> - case CHIP_DIMGREY_CAVEFISH:
> - pcache_info = dimgrey_cavefish_cache_info;
> - num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info);
> - break;
> - case CHIP_VANGOGH:
> - pcache_info = vangogh_cache_info;
> - num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
> - break;
> - case CHIP_BEIGE_GOBY:
> - pcache_info = beige_goby_cache_info;
> - num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
> - break;
> - case CHIP_YELLOW_CARP:
> - pcache_info = yellow_carp_cache_info;
> - num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
> - break;
> default:
> - return -EINVAL;
> + switch(kdev->adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + pcache_info = vega10_cache_info;
> + num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
> + break;
> + case IP_VERSION(9, 2, 1):
> + pcache_info = vega12_cache_info;
> + num_of_cache_types = ARRAY_SIZE(vega12_cache_info);
> + break;
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 4, 1):
> + pcache_info = vega20_cache_info;
> + num_of_cache_types = ARRAY_SIZE(vega20_cache_info);
> + break;
> + case IP_VERSION(9, 4, 2):
> + pcache_info = aldebaran_cache_info;
> + num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info);
> + break;
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + pcache_info = raven_cache_info;
> + num_of_cache_types = ARRAY_SIZE(raven_cache_info);
> + break;
> + case IP_VERSION(9, 3, 0):
> + pcache_info = renoir_cache_info;
> + num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
> + break;
> + case IP_VERSION(10, 1, 10):
> + case IP_VERSION(10, 1, 2):
> + case IP_VERSION(10, 1, 3):
> + pcache_info = navi10_cache_info;
> + num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
> + break;
> + case IP_VERSION(10, 1, 1):
> + pcache_info = navi14_cache_info;
> + num_of_cache_types = ARRAY_SIZE(navi14_cache_info);
> + break;
> + case IP_VERSION(10, 3, 0):
> + pcache_info = sienna_cichlid_cache_info;
> + num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info);
> + break;
> + case IP_VERSION(10, 3, 2):
> + pcache_info = navy_flounder_cache_info;
> + num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info);
> + break;
> + case IP_VERSION(10, 3, 4):
> + pcache_info = dimgrey_cavefish_cache_info;
> + num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info);
> + break;
> + case IP_VERSION(10, 3, 1):
> + pcache_info = vangogh_cache_info;
> + num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
> + break;
> + case IP_VERSION(10, 3, 5):
> + pcache_info = beige_goby_cache_info;
> + num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
> + break;
> + case IP_VERSION(10, 3, 3):
> + pcache_info = yellow_carp_cache_info;
> + num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
> + break;
> + default:
> + return -EINVAL;
> + }
> }
>
> *size_filled = 0;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index 0a60317509c8..8a39494fa093 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -1947,31 +1947,39 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
> device_queue_manager_init_vi_tonga(&dqm->asic_ops);
> break;
>
> - case CHIP_VEGA10:
> - case CHIP_VEGA12:
> - case CHIP_VEGA20:
> - case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - case CHIP_ARCTURUS:
> - case CHIP_ALDEBARAN:
> - device_queue_manager_init_v9(&dqm->asic_ops);
> - break;
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_NAVI14:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> - case CHIP_CYAN_SKILLFISH:
> - device_queue_manager_init_v10_navi10(&dqm->asic_ops);
> - break;
> default:
> - WARN(1, "Unexpected ASIC family %u",
> - dev->device_info->asic_family);
> - goto out_free;
> + switch (dev->adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + device_queue_manager_init_v9(&dqm->asic_ops);
> + break;
> + case IP_VERSION(10, 1, 10):
> + case IP_VERSION(10, 1, 2):
> + case IP_VERSION(10, 1, 1):
> + case IP_VERSION(10, 3, 0):
> + case IP_VERSION(10, 3, 2):
> + case IP_VERSION(10, 3, 1):
> + case IP_VERSION(10, 3, 4):
> + case IP_VERSION(10, 3, 5):
> + case IP_VERSION(10, 3, 3):
> + case IP_VERSION(10, 1, 3):
This could probably be replaced with an if (ip_version >= X) kind of
construct. That way you don't need to list every individual supported
chip everywhere. Minor version changes often don't require any changes
anyway. Instead of the default case, you could have a check for version
>= IP_VERSION(11,0,0) (for now) expecting that a major version bump will
probably require some attention. But minor version changes can probably
be supported without changing anything (here and many other places where
we currently have switch (asic_family).
Regards,
Felix
> + device_queue_manager_init_v10_navi10(&dqm->asic_ops);
> + break;
> + default:
> + if (dev->adev->ip_versions[GC_HWIP][0])
> + WARN(1, "Unexpected GC HWIP version %06x",
> + dev->adev->ip_versions[GC_HWIP][0]);
> + else
> + WARN(1, "Unexpected ASIC family %u",
> + dev->device_info->asic_family);
> + goto out_free;
> + }
> }
>
> if (init_mqd_managers(dqm))
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
> index 2e86692def19..6c56e43e2f7b 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
> @@ -406,29 +406,37 @@ int kfd_init_apertures(struct kfd_process *process)
> case CHIP_VEGAM:
> kfd_init_apertures_vi(pdd, id);
> break;
> - case CHIP_VEGA10:
> - case CHIP_VEGA12:
> - case CHIP_VEGA20:
> - case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - case CHIP_ARCTURUS:
> - case CHIP_ALDEBARAN:
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_NAVI14:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> - case CHIP_CYAN_SKILLFISH:
> - kfd_init_apertures_v9(pdd, id);
> - break;
> default:
> - WARN(1, "Unexpected ASIC family %u",
> - dev->device_info->asic_family);
> - return -EINVAL;
> + switch (dev->adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + case IP_VERSION(10, 1, 10):
> + case IP_VERSION(10, 1, 2):
> + case IP_VERSION(10, 1, 1):
> + case IP_VERSION(10, 3, 0):
> + case IP_VERSION(10, 3, 2):
> + case IP_VERSION(10, 3, 1):
> + case IP_VERSION(10, 3, 4):
> + case IP_VERSION(10, 3, 5):
> + case IP_VERSION(10, 3, 3):
> + case IP_VERSION(10, 1, 3):
> + kfd_init_apertures_v9(pdd, id);
> + break;
> + default:
> + if (dev->adev->ip_versions[GC_HWIP][0])
> + WARN(1, "Unexpected GC HWIP version %06x",
> + dev->adev->ip_versions[GC_HWIP][0]);
> + else
> + WARN(1, "Unexpected ASIC family %u",
> + dev->device_info->asic_family);
> + return -EINVAL;
> + }
> }
>
> if (!dev->use_iommu_v2) {
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
> index e547f1f8c49f..0bee4b965e1f 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
> @@ -236,31 +236,39 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
> case CHIP_VEGAM:
> pm->pmf = &kfd_vi_pm_funcs;
> break;
> - case CHIP_VEGA10:
> - case CHIP_VEGA12:
> - case CHIP_VEGA20:
> - case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - case CHIP_ARCTURUS:
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_NAVI14:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> - case CHIP_CYAN_SKILLFISH:
> - pm->pmf = &kfd_v9_pm_funcs;
> - break;
> - case CHIP_ALDEBARAN:
> - pm->pmf = &kfd_aldebaran_pm_funcs;
> - break;
> default:
> - WARN(1, "Unexpected ASIC family %u",
> - dqm->dev->device_info->asic_family);
> - return -EINVAL;
> + switch (dqm->dev->adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(10, 1, 10):
> + case IP_VERSION(10, 1, 2):
> + case IP_VERSION(10, 1, 1):
> + case IP_VERSION(10, 3, 0):
> + case IP_VERSION(10, 3, 2):
> + case IP_VERSION(10, 3, 1):
> + case IP_VERSION(10, 3, 4):
> + case IP_VERSION(10, 3, 5):
> + case IP_VERSION(10, 3, 3):
> + case IP_VERSION(10, 1, 3):
> + pm->pmf = &kfd_v9_pm_funcs;
> + break;
> + case IP_VERSION(9, 4, 2):
> + pm->pmf = &kfd_aldebaran_pm_funcs;
> + break;
> + default:
> + if (dqm->dev->adev->ip_versions[GC_HWIP][0])
> + WARN(1, "Unexpected GC HWIP version %06x",
> + dqm->dev->adev->ip_versions[GC_HWIP][0]);
> + else
> + WARN(1, "Unexpected ASIC family %u",
> + dqm->dev->device_info->asic_family);
> + return -EINVAL;
> + }
> }
>
> pm->dqm = dqm;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> index ae7c9944dc4a..5353f43c67f3 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> @@ -1425,30 +1425,38 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
> HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
> HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
> break;
> - case CHIP_VEGA10:
> - case CHIP_VEGA12:
> - case CHIP_VEGA20:
> - case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - case CHIP_ARCTURUS:
> - case CHIP_ALDEBARAN:
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_NAVI14:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> - case CHIP_CYAN_SKILLFISH:
> - dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
> - HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
> - HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
> - break;
> default:
> - WARN(1, "Unexpected ASIC family %u",
> - dev->gpu->device_info->asic_family);
> + switch (dev->gpu->adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + case IP_VERSION(10, 1, 10):
> + case IP_VERSION(10, 1, 2):
> + case IP_VERSION(10, 1, 1):
> + case IP_VERSION(10, 3, 0):
> + case IP_VERSION(10, 3, 2):
> + case IP_VERSION(10, 3, 1):
> + case IP_VERSION(10, 3, 4):
> + case IP_VERSION(10, 3, 5):
> + case IP_VERSION(10, 3, 3):
> + case IP_VERSION(10, 1, 3):
> + dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
> + HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
> + HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
> + break;
> + default:
> + if (dev->gpu->adev->ip_versions[GC_HWIP][0])
> + WARN(1, "Unexpected GC HWIP version %06x",
> + dev->gpu->adev->ip_versions[GC_HWIP][0]);
> + else
> + WARN(1, "Unexpected ASIC family %u",
> + dev->gpu->device_info->asic_family);
> + }
> }
>
> /*
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