[PATCH v2 3/3] drm/amdkfd: convert misc checks to IP version checking
Sider, Graham
Graham.Sider at amd.com
Wed Nov 10 16:46:38 UTC 2021
[AMD Official Use Only]
> Am 2021-11-09 um 5:42 p.m. schrieb Graham Sider:
> > Switch to IP version checking instead of asic_type on various KFD
> > version checks.
> >
> > Signed-off-by: Graham Sider <Graham.Sider at amd.com>
> > ---
> > drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +-
> > drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
> > drivers/gpu/drm/amd/amdkfd/kfd_device.c | 27 ++++++++++---------
> > .../drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +--
> > .../amd/amdkfd/kfd_device_queue_manager_v9.c | 2 +-
> > drivers/gpu/drm/amd/amdkfd/kfd_events.c | 6 +++--
> > drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
> > drivers/gpu/drm/amd/amdkfd/kfd_process.c | 7 +++--
> > drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 6 ++---
> > drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 +--
> > 10 files changed, 31 insertions(+), 30 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > index 2466a73b8c7d..f70117b00b14 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> > @@ -1603,7 +1603,7 @@ static int
> kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
> > }
> > mutex_unlock(&p->mutex);
> >
> > - if (dev->device_info->asic_family == CHIP_ALDEBARAN) {
> > + if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) {
> > err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev,
> > (struct kgd_mem *) mem, true);
> > if (err) {
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > index 19dd472e9b06..b6d887edac85 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> > @@ -1992,7 +1992,7 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int
> *avail_size,
> > sub_type_hdr->flags |=
> CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
> > sub_type_hdr->io_interface_type =
> CRAT_IOLINK_TYPE_XGMI;
> > sub_type_hdr->num_hops_xgmi = 1;
> > - if (kdev->adev->asic_type == CHIP_ALDEBARAN) {
> > + if (KFD_GC_VERSION(kdev) == IP_VERSION(9, 4, 2)) {
> > sub_type_hdr->minimum_bandwidth_mbs =
> >
> amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(
> > kdev->adev, NULL,
> true);
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> > index ee813bd57c92..594dd28a391f 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> > @@ -848,23 +848,23 @@ struct kfd_dev *kgd2kfd_probe(struct
> > amdgpu_device *adev, bool vf) static void kfd_cwsr_init(struct
> > kfd_dev *kfd) {
> > if (cwsr_enable && kfd->device_info->supports_cwsr) {
> > - if (kfd->device_info->asic_family < CHIP_VEGA10) {
> > + if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
> > BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) >
> PAGE_SIZE);
> > kfd->cwsr_isa = cwsr_trap_gfx8_hex;
> > kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
> > - } else if (kfd->device_info->asic_family == CHIP_ARCTURUS)
> {
> > + } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
> > BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) >
> PAGE_SIZE);
> > kfd->cwsr_isa = cwsr_trap_arcturus_hex;
> > kfd->cwsr_isa_size =
> sizeof(cwsr_trap_arcturus_hex);
> > - } else if (kfd->device_info->asic_family ==
> CHIP_ALDEBARAN) {
> > + } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
> > BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) >
> PAGE_SIZE);
> > kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
> > kfd->cwsr_isa_size =
> sizeof(cwsr_trap_aldebaran_hex);
> > - } else if (kfd->device_info->asic_family < CHIP_NAVI10) {
> > + } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
> > BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) >
> PAGE_SIZE);
> > kfd->cwsr_isa = cwsr_trap_gfx9_hex;
> > kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
> > - } else if (kfd->device_info->asic_family <
> CHIP_SIENNA_CICHLID) {
> > + } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
> > BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) >
> PAGE_SIZE);
> > kfd->cwsr_isa = cwsr_trap_nv1x_hex;
> > kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
> @@ -886,14
> > +886,16 @@ static int kfd_gws_init(struct kfd_dev *kfd)
> > return 0;
> >
> > if (hws_gws_support
> > - || (kfd->device_info->asic_family == CHIP_VEGA10
> > + || (KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1)
> > && kfd->mec2_fw_version >= 0x81b3)
> > - || (kfd->device_info->asic_family >= CHIP_VEGA12
> > - && kfd->device_info->asic_family <= CHIP_RAVEN
> > + || ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 2, 1)
> > + || KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 0)
> > + || KFD_GC_VERSION(kfd) == IP_VERSION(9, 1, 0)
> > + || KFD_GC_VERSION(kfd) == IP_VERSION(9, 2, 2))
>
> I think this could be simplified to KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4,
> 0) if it weren't for Renoir. I wonder if the exclusion of RENOIR was an
> oversight in the old code due to the weird ordering of the CHIP_...
> enums. Let me start an internal email thread to confirm.
>
>
That would make sense, I agree this part caught me as a little strange--sounds good.
> > && kfd->mec2_fw_version >= 0x1b3)
> > - || (kfd->device_info->asic_family == CHIP_ARCTURUS
> > + || (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)
> > && kfd->mec2_fw_version >= 0x30)
> > - || (kfd->device_info->asic_family == CHIP_ALDEBARAN
> > + || (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)
> > && kfd->mec2_fw_version >= 0x28))
> > ret = amdgpu_amdkfd_alloc_gws(kfd->adev,
> > kfd->adev->gds.gws_size, &kfd->gws); @@ -
> 962,10 +964,9 @@ bool
> > kgd2kfd_device_init(struct kfd_dev *kfd,
> > * calculate max size of runlist packet.
> > * There can be only 2 packets at once
> > */
> > - map_process_packet_size =
> > - kfd->device_info->asic_family == CHIP_ALDEBARAN
> ?
> > + map_process_packet_size = KFD_GC_VERSION(kfd) ==
> IP_VERSION(9, 4, 2) ?
> > sizeof(struct
> pm4_mes_map_process_aldebaran) :
> > - sizeof(struct
> pm4_mes_map_process);
> > + sizeof(struct pm4_mes_map_process);
> > size += (KFD_MAX_NUM_OF_PROCESSES *
> map_process_packet_size +
> > max_num_of_queues_per_device * sizeof(struct
> pm4_mes_map_queues)
> > + sizeof(struct pm4_mes_runlist)) * 2; diff --git
> > a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > index 93d41e0b9b41..c894cbe58a36 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > @@ -250,8 +250,7 @@ static int allocate_vmid(struct
> > device_queue_manager *dqm,
> >
> > program_sh_mem_settings(dqm, qpd);
> >
> > - if (dqm->dev->device_info->asic_family >= CHIP_VEGA10 &&
> > - dqm->dev->cwsr_enabled)
> > + if (KFD_IS_SOC15(dqm->dev) && dqm->dev->cwsr_enabled)
> > program_trap_handler_settings(dqm, qpd);
> >
> > /* qpd->page_table_base is set earlier when register_process() diff
> > --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
> > index b5c3d13643f1..f20434d9980e 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
> > @@ -62,7 +62,7 @@ static int update_qpd_v9(struct
> device_queue_manager *dqm,
> > SH_MEM_ALIGNMENT_MODE_UNALIGNED
> <<
> >
> SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
> >
> > - if (dqm->dev->device_info->asic_family ==
> CHIP_ALDEBARAN) {
> > + if (KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 2)) {
> > /* Aldebaran can safely support different XNACK
> modes
> > * per process
> > */
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
> > index 3eea4edee355..afe72dd11325 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
> > @@ -935,8 +935,10 @@ void kfd_signal_iommu_event(struct kfd_dev
> *dev, u32 pasid,
> > /* Workaround on Raven to not kill the process when memory is
> freed
> > * before IOMMU is able to finish processing all the excessive PPRs
> > */
> > - if (dev->device_info->asic_family != CHIP_RAVEN &&
> > - dev->device_info->asic_family != CHIP_RENOIR) {
> > +
> > + if (KFD_GC_VERSION(dev) != IP_VERSION(9, 1, 0) &&
> > + KFD_GC_VERSION(dev) != IP_VERSION(9, 2, 2) &&
> > + KFD_GC_VERSION(dev) != IP_VERSION(9, 3, 0)) {
> > mutex_lock(&p->event_mutex);
> >
> > /* Lookup events by type and signal them */ diff --git
> > a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> > index aeade32ec298..d59b73f69260 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> > @@ -940,7 +940,7 @@ int svm_migrate_init(struct amdgpu_device *adev)
> > void *r;
> >
> > /* Page migration works on Vega10 or newer */
> > - if (kfddev->device_info->asic_family < CHIP_VEGA10)
> > + if (!KFD_IS_SOC15(kfddev))
> > return -EINVAL;
> >
> > pgmap = &kfddev->pgmap;
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> > index fafc7b187fad..74c9323f32fc 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> > @@ -1317,14 +1317,13 @@ bool kfd_process_xnack_mode(struct
> kfd_process *p, bool supported)
> > * support the SVM APIs and don't need to be considered
> > * for the XNACK mode selection.
> > */
> > - if (dev->device_info->asic_family < CHIP_VEGA10)
> > + if (!KFD_IS_SOC15(dev))
> > continue;
> > /* Aldebaran can always support XNACK because it can
> support
> > * per-process XNACK mode selection. But let the dev-
> >noretry
> > * setting still influence the default XNACK mode.
> > */
> > - if (supported &&
> > - dev->device_info->asic_family == CHIP_ALDEBARAN)
> > + if (supported && KFD_GC_VERSION(dev) == IP_VERSION(9,
> 4, 2))
> > continue;
> >
> > /* GFXv10 and later GPUs do not support shader preemption
> @@
> > -1332,7 +1331,7 @@ bool kfd_process_xnack_mode(struct kfd_process *p,
> bool supported)
> > * management and memory-manager-related preemptions
> or
> > * even deadlocks.
> > */
> > - if (dev->device_info->asic_family >= CHIP_NAVI10)
> > + if (KFD_GC_VERSION(dev) > IP_VERSION(10, 1, 1))
>
> This should be >=
>
> Regards,
> Felix
>
>
Good catch, thanks!
Best,
Graham
> > return false;
> >
> > if (dev->noretry)
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> > index 77239b06b236..88360f23eb61 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> > @@ -1051,8 +1051,8 @@ svm_range_get_pte_flags(struct amdgpu_device
> *adev, struct svm_range *prange,
> > if (domain == SVM_RANGE_VRAM_DOMAIN)
> > bo_adev = amdgpu_ttm_adev(prange->svm_bo->bo-
> >tbo.bdev);
> >
> > - switch (adev->asic_type) {
> > - case CHIP_ARCTURUS:
> > + switch (KFD_GC_VERSION(adev->kfd.dev)) {
> > + case IP_VERSION(9, 4, 1):
> > if (domain == SVM_RANGE_VRAM_DOMAIN) {
> > if (bo_adev == adev) {
> > mapping_flags |= coherent ?
> > @@ -1068,7 +1068,7 @@ svm_range_get_pte_flags(struct amdgpu_device
> *adev, struct svm_range *prange,
> > AMDGPU_VM_MTYPE_UC :
> AMDGPU_VM_MTYPE_NC;
> > }
> > break;
> > - case CHIP_ALDEBARAN:
> > + case IP_VERSION(9, 4, 2):
> > if (domain == SVM_RANGE_VRAM_DOMAIN) {
> > if (bo_adev == adev) {
> > mapping_flags |= coherent ?
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > index a4c0c929444a..641e250dc95f 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> > @@ -1239,7 +1239,7 @@ static void kfd_set_iolink_non_coherent(struct
> kfd_topology_device *to_dev,
> > */
> > if (inbound_link->iolink_type ==
> CRAT_IOLINK_TYPE_PCIEXPRESS ||
> > (inbound_link->iolink_type == CRAT_IOLINK_TYPE_XGMI
> &&
> > - to_dev->gpu->device_info->asic_family ==
> CHIP_VEGA20)) {
> > + KFD_GC_VERSION(to_dev->gpu) == IP_VERSION(9, 4, 0)))
> {
> > outbound_link->flags |=
> CRAT_IOLINK_FLAGS_NON_COHERENT;
> > inbound_link->flags |=
> CRAT_IOLINK_FLAGS_NON_COHERENT;
> > }
> > @@ -1463,7 +1463,7 @@ int kfd_topology_add_device(struct kfd_dev
> *gpu)
> > ((dev->gpu->adev->ras_enabled &
> BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
> > HSA_CAP_MEM_EDCSUPPORTED : 0;
> >
> > - if (dev->gpu->adev->asic_type != CHIP_VEGA10)
> > + if (KFD_GC_VERSION(dev->gpu) != IP_VERSION(9, 0, 1))
> > dev->node_props.capability |= (dev->gpu->adev-
> >ras_enabled != 0) ?
> > HSA_CAP_RASEVENTNOTIFY : 0;
> >
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