[PATCH 5/9] drm/amdgpu: Modify mca block to fit for the unified ras function pointers.

[yipechai]

Modify mca block ras functions to fit for the unified ras function pointers.

Signed-off-by: yipechai <YiPeng.Chai at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 12 +++++-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h |  8 ++-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 12 +++++-----
 drivers/gpu/drm/amd/amdgpu/mca_v3_0.c   | 30 +++++++++++++++----------
 4 files changed, 32 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 0aab31fce997..024342969267 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -466,22 +466,22 @@ int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
 	}
 
 	if (adev->mca.mp0.ras_funcs &&
-	    adev->mca.mp0.ras_funcs->ras_late_init) {
-		r = adev->mca.mp0.ras_funcs->ras_late_init(adev);
+	    adev->mca.mp0.ras_funcs->ops.ras_late_init) {
+		r = adev->mca.mp0.ras_funcs->ops.ras_late_init(adev);
 		if (r)
 			return r;
 	}
 
 	if (adev->mca.mp1.ras_funcs &&
-	    adev->mca.mp1.ras_funcs->ras_late_init) {
-		r = adev->mca.mp1.ras_funcs->ras_late_init(adev);
+	    adev->mca.mp1.ras_funcs->ops.ras_late_init) {
+		r = adev->mca.mp1.ras_funcs->ops.ras_late_init(adev);
 		if (r)
 			return r;
 	}
 
 	if (adev->mca.mpio.ras_funcs &&
-	    adev->mca.mpio.ras_funcs->ras_late_init) {
-		r = adev->mca.mpio.ras_funcs->ras_late_init(adev);
+	    adev->mca.mpio.ras_funcs->ops.ras_late_init) {
+		r = adev->mca.mpio.ras_funcs->ops.ras_late_init(adev);
 		if (r)
 			return r;
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h
index c74bc7177066..fbc3ebc81b99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h
@@ -20,14 +20,10 @@
  */
 #ifndef __AMDGPU_MCA_H__
 #define __AMDGPU_MCA_H__
+#include "amdgpu_ras.h"
 
 struct amdgpu_mca_ras_funcs {
-	int (*ras_late_init)(struct amdgpu_device *adev);
-	void (*ras_fini)(struct amdgpu_device *adev);
-	void (*query_ras_error_count)(struct amdgpu_device *adev,
-				      void *ras_error_status);
-	void (*query_ras_error_address)(struct amdgpu_device *adev,
-					void *ras_error_status);
+	struct amdgpu_ras_block_ops ops;
 	uint32_t ras_block;
 	uint32_t ras_sub_block;
 	const char* sysfs_name;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index a3b606c84d45..e7cd2de07665 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -870,18 +870,18 @@ void amdgpu_ras_mca_query_error_status(struct amdgpu_device *adev,
 	switch (ras_block->sub_block_index) {
 	case AMDGPU_RAS_MCA_BLOCK__MP0:
 		if (adev->mca.mp0.ras_funcs &&
-		    adev->mca.mp0.ras_funcs->query_ras_error_count)
-			adev->mca.mp0.ras_funcs->query_ras_error_count(adev, &err_data);
+		    adev->mca.mp0.ras_funcs->ops.query_ras_error_count)
+			adev->mca.mp0.ras_funcs->ops.query_ras_error_count(adev, &err_data);
 		break;
 	case AMDGPU_RAS_MCA_BLOCK__MP1:
 		if (adev->mca.mp1.ras_funcs &&
-		    adev->mca.mp1.ras_funcs->query_ras_error_count)
-			adev->mca.mp1.ras_funcs->query_ras_error_count(adev, &err_data);
+		    adev->mca.mp1.ras_funcs->ops.query_ras_error_count)
+			adev->mca.mp1.ras_funcs->ops.query_ras_error_count(adev, &err_data);
 		break;
 	case AMDGPU_RAS_MCA_BLOCK__MPIO:
 		if (adev->mca.mpio.ras_funcs &&
-		    adev->mca.mpio.ras_funcs->query_ras_error_count)
-			adev->mca.mpio.ras_funcs->query_ras_error_count(adev, &err_data);
+		    adev->mca.mpio.ras_funcs->ops.query_ras_error_count)
+			adev->mca.mpio.ras_funcs->ops.query_ras_error_count(adev, &err_data);
 		break;
 	default:
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/mca_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mca_v3_0.c
index 8f7107d392af..dc2424587f12 100644
--- a/drivers/gpu/drm/amd/amdgpu/mca_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mca_v3_0.c
@@ -48,10 +48,12 @@ static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev)
 }
 
 const struct amdgpu_mca_ras_funcs mca_v3_0_mp0_ras_funcs = {
-	.ras_late_init = mca_v3_0_mp0_ras_late_init,
-	.ras_fini = mca_v3_0_mp0_ras_fini,
-	.query_ras_error_count = mca_v3_0_mp0_query_ras_error_count,
-	.query_ras_error_address = NULL,
+	.ops = {
+		.ras_late_init = mca_v3_0_mp0_ras_late_init,
+		.ras_fini = mca_v3_0_mp0_ras_fini,
+		.query_ras_error_count = mca_v3_0_mp0_query_ras_error_count,
+		.query_ras_error_address = NULL,
+	},
 	.ras_block = AMDGPU_RAS_BLOCK__MCA,
 	.ras_sub_block = AMDGPU_RAS_MCA_BLOCK__MP0,
 	.sysfs_name = "mp0_err_count",
@@ -76,10 +78,12 @@ static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev)
 }
 
 const struct amdgpu_mca_ras_funcs mca_v3_0_mp1_ras_funcs = {
-	.ras_late_init = mca_v3_0_mp1_ras_late_init,
-	.ras_fini = mca_v3_0_mp1_ras_fini,
-	.query_ras_error_count = mca_v3_0_mp1_query_ras_error_count,
-	.query_ras_error_address = NULL,
+	.ops = {
+		.ras_late_init = mca_v3_0_mp1_ras_late_init,
+		.ras_fini = mca_v3_0_mp1_ras_fini,
+		.query_ras_error_count = mca_v3_0_mp1_query_ras_error_count,
+		.query_ras_error_address = NULL,
+	},
 	.ras_block = AMDGPU_RAS_BLOCK__MCA,
 	.ras_sub_block = AMDGPU_RAS_MCA_BLOCK__MP1,
 	.sysfs_name = "mp1_err_count",
@@ -104,10 +108,12 @@ static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev)
 }
 
 const struct amdgpu_mca_ras_funcs mca_v3_0_mpio_ras_funcs = {
-	.ras_late_init = mca_v3_0_mpio_ras_late_init,
-	.ras_fini = mca_v3_0_mpio_ras_fini,
-	.query_ras_error_count = mca_v3_0_mpio_query_ras_error_count,
-	.query_ras_error_address = NULL,
+	.ops = {
+		.ras_late_init = mca_v3_0_mpio_ras_late_init,
+		.ras_fini = mca_v3_0_mpio_ras_fini,
+		.query_ras_error_count = mca_v3_0_mpio_query_ras_error_count,
+		.query_ras_error_address = NULL,
+	},
 	.ras_block = AMDGPU_RAS_BLOCK__MCA,
 	.ras_sub_block = AMDGPU_RAS_MCA_BLOCK__MPIO,
 	.sysfs_name = "mpio_err_count",
-- 
2.25.1