[PATCH] drm/amdgpu/pm: properly handle sclk for profiling modes on vangogh
Quan, Evan
Evan.Quan at amd.com
Tue Oct 12 01:24:27 UTC 2021
[AMD Official Use Only]
Reviewed-by: Evan Quan <evan.quan at amd.com>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Monday, October 11, 2021 11:04 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
> Subject: [PATCH] drm/amdgpu/pm: properly handle sclk for profiling modes
> on vangogh
>
> When selecting between levels in the force performance levels interface sclk
> (gfxclk) was not set correctly for all levels. Select the proper sclk settings for
> all levels.
>
> Bug:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitla
> b.freedesktop.org%2Fdrm%2Famd%2F-
> %2Fissues%2F1726&data=04%7C01%7Cevan.quan%40amd.com%7C3bf
> 2cf5224d4467295e508d98cc85ebf%7C3dd8961fe4884e608e11a82d994e183d%
> 7C0%7C0%7C637695614479890816%7CUnknown%7CTWFpbGZsb3d8eyJWIjoi
> MC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C100
> 0&sdata=nnWeLhX6hPmlP42pH9ygjiLX44HIzPApyR0%2BIFh5oaQ%3D&a
> mp;reserved=0
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 89 ++++++------------
> -
> 1 file changed, 29 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index bdd1a01e27b4..8d5f32807821 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -1386,52 +1386,38 @@ static int vangogh_set_performance_level(struct
> smu_context *smu,
> uint32_t soc_mask, mclk_mask, fclk_mask;
> uint32_t vclk_mask = 0, dclk_mask = 0;
>
> + smu->cpu_actual_soft_min_freq = smu-
> >cpu_default_soft_min_freq;
> + smu->cpu_actual_soft_max_freq = smu-
> >cpu_default_soft_max_freq;
> +
> switch (level) {
> case AMD_DPM_FORCED_LEVEL_HIGH:
> - smu->gfx_actual_hard_min_freq = smu-
> >gfx_default_hard_min_freq;
> + smu->gfx_actual_hard_min_freq = smu-
> >gfx_default_soft_max_freq;
> smu->gfx_actual_soft_max_freq = smu-
> >gfx_default_soft_max_freq;
>
> - smu->cpu_actual_soft_min_freq = smu-
> >cpu_default_soft_min_freq;
> - smu->cpu_actual_soft_max_freq = smu-
> >cpu_default_soft_max_freq;
>
> ret = vangogh_force_dpm_limit_value(smu, true);
> + if (ret)
> + return ret;
> break;
> case AMD_DPM_FORCED_LEVEL_LOW:
> smu->gfx_actual_hard_min_freq = smu-
> >gfx_default_hard_min_freq;
> - smu->gfx_actual_soft_max_freq = smu-
> >gfx_default_soft_max_freq;
> -
> - smu->cpu_actual_soft_min_freq = smu-
> >cpu_default_soft_min_freq;
> - smu->cpu_actual_soft_max_freq = smu-
> >cpu_default_soft_max_freq;
> + smu->gfx_actual_soft_max_freq = smu-
> >gfx_default_hard_min_freq;
>
> ret = vangogh_force_dpm_limit_value(smu, false);
> + if (ret)
> + return ret;
> break;
> case AMD_DPM_FORCED_LEVEL_AUTO:
> smu->gfx_actual_hard_min_freq = smu-
> >gfx_default_hard_min_freq;
> smu->gfx_actual_soft_max_freq = smu-
> >gfx_default_soft_max_freq;
>
> - smu->cpu_actual_soft_min_freq = smu-
> >cpu_default_soft_min_freq;
> - smu->cpu_actual_soft_max_freq = smu-
> >cpu_default_soft_max_freq;
> -
> ret = vangogh_unforce_dpm_levels(smu);
> - break;
> - case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> - smu->gfx_actual_hard_min_freq = smu-
> >gfx_default_hard_min_freq;
> - smu->gfx_actual_soft_max_freq = smu-
> >gfx_default_soft_max_freq;
> -
> - smu->cpu_actual_soft_min_freq = smu-
> >cpu_default_soft_min_freq;
> - smu->cpu_actual_soft_max_freq = smu-
> >cpu_default_soft_max_freq;
> -
> - ret = smu_cmn_send_smc_msg_with_param(smu,
> - SMU_MSG_SetHardMinGfxClk,
> -
> VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
> - if (ret)
> - return ret;
> -
> - ret = smu_cmn_send_smc_msg_with_param(smu,
> - SMU_MSG_SetSoftMaxGfxClk,
> -
> VANGOGH_UMD_PSTATE_STANDARD_GFXCLK, NULL);
> if (ret)
> return ret;
> + break;
> + case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> + smu->gfx_actual_hard_min_freq =
> VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
> + smu->gfx_actual_soft_max_freq =
> VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
>
> ret = vangogh_get_profiling_clk_mask(smu, level,
> &vclk_mask,
> @@ -1446,32 +1432,15 @@ static int vangogh_set_performance_level(struct
> smu_context *smu,
> vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 <<
> soc_mask);
> vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
> vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
> -
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> smu->gfx_actual_hard_min_freq = smu-
> >gfx_default_hard_min_freq;
> - smu->gfx_actual_soft_max_freq = smu-
> >gfx_default_soft_max_freq;
> -
> - smu->cpu_actual_soft_min_freq = smu-
> >cpu_default_soft_min_freq;
> - smu->cpu_actual_soft_max_freq = smu-
> >cpu_default_soft_max_freq;
> -
> - ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetHardMinVcn,
> -
> VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
> - if (ret)
> - return ret;
> -
> - ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetSoftMaxVcn,
> -
> VANGOGH_UMD_PSTATE_PEAK_DCLK, NULL);
> - if (ret)
> - return ret;
> + smu->gfx_actual_soft_max_freq = smu-
> >gfx_default_hard_min_freq;
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> smu->gfx_actual_hard_min_freq = smu-
> >gfx_default_hard_min_freq;
> smu->gfx_actual_soft_max_freq = smu-
> >gfx_default_soft_max_freq;
>
> - smu->cpu_actual_soft_min_freq = smu-
> >cpu_default_soft_min_freq;
> - smu->cpu_actual_soft_max_freq = smu-
> >cpu_default_soft_max_freq;
> -
> ret = vangogh_get_profiling_clk_mask(smu, level,
> NULL,
> NULL,
> @@ -1484,29 +1453,29 @@ static int vangogh_set_performance_level(struct
> smu_context *smu,
> vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
> break;
> case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> - smu->gfx_actual_hard_min_freq = smu-
> >gfx_default_hard_min_freq;
> - smu->gfx_actual_soft_max_freq = smu-
> >gfx_default_soft_max_freq;
> -
> - smu->cpu_actual_soft_min_freq = smu-
> >cpu_default_soft_min_freq;
> - smu->cpu_actual_soft_max_freq = smu-
> >cpu_default_soft_max_freq;
> -
> - ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetHardMinGfxClk,
> - VANGOGH_UMD_PSTATE_PEAK_GFXCLK,
> NULL);
> - if (ret)
> - return ret;
> + smu->gfx_actual_hard_min_freq =
> VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
> + smu->gfx_actual_soft_max_freq =
> VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
>
> - ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetSoftMaxGfxClk,
> - VANGOGH_UMD_PSTATE_PEAK_GFXCLK,
> NULL);
> + ret = vangogh_set_peak_clock_by_device(smu);
> if (ret)
> return ret;
> -
> - ret = vangogh_set_peak_clock_by_device(smu);
> break;
> case AMD_DPM_FORCED_LEVEL_MANUAL:
> case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
> default:
> - break;
> + return 0;
> }
> +
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetHardMinGfxClk,
> + smu->gfx_actual_hard_min_freq,
> NULL);
> + if (ret)
> + return ret;
> +
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetSoftMaxGfxClk,
> + smu->gfx_actual_soft_max_freq,
> NULL);
> + if (ret)
> + return ret;
> +
> return ret;
> }
>
> --
> 2.31.1
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