[PATCH] drm/amdgpu/nbio2.3: use original HDP_FLUSH bits for navi1x

[Alex Deucher]

On Wed, Oct 13, 2021 at 11:06 AM Alex Deucher <alexander.deucher at amd.com> wrote:
>
> The extended bits were not available for use on navi1x, but
> navi2x only have 2 sdma instances so we won't conflict with

This should say navi1x.  Fixed locally.

Alex

> firmware anyway.
>
> Fixes: 468e994c41ecb3 ("drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit 12")
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |  5 ++++-
>  drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c        | 15 +++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h        |  1 +
>  3 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 4228c7964175..9645b95b9c42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1133,12 +1133,15 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
>         case IP_VERSION(2, 3, 0):
>         case IP_VERSION(2, 3, 1):
>         case IP_VERSION(2, 3, 2):
> +               adev->nbio.funcs = &nbio_v2_3_funcs;
> +               adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
> +               break;
>         case IP_VERSION(3, 3, 0):
>         case IP_VERSION(3, 3, 1):
>         case IP_VERSION(3, 3, 2):
>         case IP_VERSION(3, 3, 3):
>                 adev->nbio.funcs = &nbio_v2_3_funcs;
> -               adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
> +               adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
>                 break;
>         default:
>                 break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> index 79bf6b381862..4ecd2b5808ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> @@ -314,6 +314,21 @@ static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev)
>  }
>
>  const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = {
> +       .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,
> +       .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK,
> +       .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK,
> +       .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK,
> +       .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK,
> +       .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK,
> +       .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK,
> +       .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK,
> +       .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK,
> +       .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK,
> +       .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
> +       .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
> +};
> +
> +const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg_sc = {
>         .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,
>         .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK,
>         .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK,
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
> index a43b60acf7f6..6074dd3a1ed8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
> @@ -27,6 +27,7 @@
>  #include "soc15_common.h"
>
>  extern const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg;
> +extern const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg_sc;
>  extern const struct amdgpu_nbio_funcs nbio_v2_3_funcs;
>
>  #endif
> --
> 2.31.1
>