[PATCH] drm/amdgpu: use correct register mask to extract field

[Zhang, Hawking]

[AMD Official Use Only]

Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>

Regards,
Hawking
-----Original Message-----
From: Wang, Yang(Kevin) <KevinYang.Wang at amd.com>
Sent: Friday, October 29, 2021 15:17
To: amd-gfx at lists.freedesktop.org
Cc: Zhang, Hawking <Hawking.Zhang at amd.com>; Min, Frank <Frank.Min at amd.com>; Lazar, Lijo <Lijo.Lazar at amd.com>; Oak Zeng <Oak.Zeng at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>
Subject: [PATCH] drm/amdgpu: use correct register mask to extract field

From: Oak Zeng <Oak.Zeng at amd.com>

Aldebaran has different register mask definitions for regiter MC_VM_XGMI_LFB_CNTL. Use the correct masks to interpret fields of this register.

Signed-off-by: Oak Zeng <Oak.Zeng at amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
index 497b86c376c6..90f0aefbdb39 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
@@ -54,15 +54,17 @@ int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
                seg_size = REG_GET_FIELD(
                        RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE),
                        MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
+               max_region =
+                       REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE,
+PF_MAX_REGION);
        } else {
                xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
                seg_size = REG_GET_FIELD(
                        RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
                        MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
+               max_region =
+                       REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
        }

-       max_region =
-               REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);


        switch (adev->asic_type) {
@@ -89,9 +91,15 @@ int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
                if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
                        return -EINVAL;

-               adev->gmc.xgmi.physical_node_id =
-               REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
-                             PF_LFB_REGION);
+               if (adev->asic_type == CHIP_ALDEBARAN) {
+                       adev->gmc.xgmi.physical_node_id =
+                               REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE,
+                                               PF_LFB_REGION);
+               } else {
+                       adev->gmc.xgmi.physical_node_id =
+                               REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
+                                               PF_LFB_REGION);
+               }

                if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
                        return -EINVAL;
--
2.25.1